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TDA4VH-Q1: TDA4VH - C7x - Normal DMA channel

Gowtham R
Intellectual 320 points

Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: SYSCONFIG

Hi TI team,

SDK - 11

Boot Sequence - SPL

I am trying to increase the number of channels for Block copy using sysconfig tool and did make u-boot using top level make file in linux sdk

 

image.png

I am getting error in c7x 

image.png

how to solve this

 

Thanks

Regards

Gowtham

  • 0
    TI__Guru*** 127605 points

    Hi Gowtham,

    Please expect a delay in response until next week due to the US Thanksgiving Holidays.

    regards

    Suman

  • 0 in reply to Suman Anna
    TI__Mastermind 29020 points

    Hi ,

    Can you send your .syscfg file that you used to generate the .yaml files?

    It looks like the Udma_chPair function is failing. I assume you removed a channel from the C7x1 to compensate.

    Additionally, why do you need to increase the block copy channels?

    Best,
    Jared

  • 0 in reply to Jared McArthur
    Intellectual 320 points

    It looks like the Udma_chPair function is failing. I assume you removed a channel from C7x1 to compensate.

    • I removed a channel from A72 and added it here.

    Additionally, why do you need to increase the block copy channels?

    • The issue is that when we run TIDL on C7x_0 and C7x_1, I think it uses DRU channels.

    My firmware runs on C7x_2 and C7x_3, and it also uses DRU channels for DMA.

    We have configured DRU channels as follows:
    C7x_0 – 8, C7x_1 – 8, C7x_2 – 6, and C7x_3 – 4.
    These are our DMA DRU channel configurations. When TIDL runs on Core_0 and Core_1, our DMA crashes on C7x_2 and C7x_3.

    My question is: when TIDL runs on C7x_0 and C7x_1, it uses only 16 DMA DRU channels. Will this affect the 10 DMA DRU channels allocated to C7x_2 and C7x_3?

  • 0 in reply to Gowtham R
    TI__Mastermind 29020 points

    Hi ,

    I've assigned our C7x expert who will be able to better assist you.

    Best,
    Jared

  • 0 in reply to Jared McArthur
    TI__Expert 8650 points

    Hi,

    Gowtham R said:
    We have configured DRU channels as follows:
    C7x_0 – 8, C7x_1 – 8, C7x_2 – 6, and C7x_3 – 4.
    These are our DMA DRU channel configurations. When TIDL runs on Core_0 and Core_1, our DMA crashes on C7x_2 and C7x_3.

    Did you make modifications to the ring accelerator count as well?

    Gowtham R said:
    My question is: when TIDL runs on C7x_0 and C7x_1, it uses only 16 DMA DRU channels. Will this affect the 10 DMA DRU channels allocated to C7x_2 and C7x_3?

    Since they are using different channels, no.

    Regards,
    Sivadeep

  • 0 in reply to Sivadeep P R
    Intellectual 320 points

    Did you make modifications to the ring accelerator count as well?

    - No, I didn't make any.

    What's the difference between DRU channels and normal DMA channels?

    1) These DRU channel Management is done by DMSC firmware? and all these will have one channel manager across cores, and these are requested via MCU1_0 to DMSC for channel allocation? 

  • 0 in reply to Gowtham R
    TI__Expert 8650 points

    Hi,

    Gowtham R said:
    What's the difference between DRU channels and normal DMA channels?

    DRU is preferred data mover for C7x-specific high-performance task (C7x/MMA deep learning operations).

    I'm checking the other questions internally. 

    Regards,
    Sivadeep

  • 0 in reply to Gowtham R
    TI__Intellectual 1910 points

    Hi,
    DRU channel management is performed by DMSC only at boot time using boardcfg_rm.

    Regards,

    Ben Eapen Thomas

  • 0 in reply to Ben Thomas
    Intellectual 320 points

    Hi , Thanks for the response.

    So, at boot stage itself the channel will be allocated. And regarding my issue on TIDL running on C7x_0 and C7x_1 and sample apps that has dru dma running on C7x_2 and C7x_3. If TIDL runs will that affect my DMA using DRU channels in my last two cores which does, consider its copying data from DDR to L2. 

  • 0 in reply to Gowtham R
    TI__Intellectual 1910 points

    Hi,
    I am checking this internally and will get back to you.
    Regards,
    Ben Eapen Thomas

  • 0 in reply to Ben Thomas
    TI__Expert 8650 points

    Hi,

    Apologies for the late reply. Is the issue still there?

    Gowtham R said:
    If TIDL runs will that affect my DMA using DRU channels in my last two cores which does, consider its copying data from DDR to L2. 

    Currently investigating using the scenario of using TIDL DRU and other DRU channel in c7x_2 and c7x_3 but I think you are using non DRU channel for c7x_2 and c7x_3 right, which should not cause any issues.

    Regards,
    Sivadeep