Part Number: DRA821U
Other Parts Discussed in Thread: DRA821
Hi team,
We are beginning to evaluate the full debug workflow for the DRA821U SoC.
Our goal is to better understand how to debug the boot process, as well as how to develop and debug custom firmware for the R5F cores on our custom board. We also have the J7200 EVM kit, so our intention is to start experimenting there using the on-board XDS110 debugger before moving to our custom HW.
We have reviewed the documentation in both the Processor SDK Linux and Processor SDK RTOS, but the overall process still isn’t fully clear to us.
We would appreciate guidance on the following points:
- Debugging the boot process (ROM → tiboot3.bin → tispl.bin → u-boot.img → Linux)
- What is the recommended method to load and debug the bootloader components using CCS and the on-board XDS110 USB debugger?
- Is it possible to single-step through tiboot3, tispl.bin and U-Boot execution all the way until Linux starts on the A72? - Developing and debugging custom firmware on the R5F cores
- What is the correct workflow for loading and debugging R5F firmware during development?
- Can we independently load and debug R5F firmware using CCS while Linux is running on the A72?
- Is there any recommended method for coordinating Linux-side remoteproc with CCS debugging?
- User-space application development on A72 (Linux)
- Linux user-space debugging is supported with CCS?
- If so, what is the recommended workflow? - Recommended CCS version
- The documentation from the Linux SDK and the RTOS SDK seems to reference different CCS versions.
- Which CCS version do you recommend for DRA821U development today?
- Can we use the latest CCS release? We would like to use the VSCode based version.
Finally, if there is a more complete or step-by-step guide covering the above topics (early bootloader debug, R5F firmware development and debug, and Linux integration), we would greatly appreciate a pointer to it.
Thanks a lot for your support.















