Part Number: SK-TDA4VM
I am trying to route the MCSPI5 interrupt (intr_spi 0) to MCU1_0 on a J721E system running PSDK RTOS 09.02.00.05 (It's a custom board)
According to the TISCI interrupt configuration tables here:
https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721e/interrupt_cfg.html
I found:
MAIN2MCU_LVL_INTRTR0 input index 53 ← MCSPI5 intr_spi 0
MAIN2MCU_LVL_INTRTR0 output index 53 → MCU_R5FSS0_CORE0 interrupt 213
My code:
static int32_t intern_CfgIrqRouter(uint32_t src_dev,
uint32_t offset,
uint32_t dest_dev,
uint32_t intNum)
{
struct tisci_msg_rm_irq_set_req rmIrqReq = {0};
struct tisci_msg_rm_irq_set_resp rmIrqResp = {0};
rmIrqReq.valid_params = TISCI_MSG_VALUE_RM_DST_ID_VALID |
TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
rmIrqReq.src_id = src_dev; /* TISCI_DEV_MCSPI5 */
rmIrqReq.src_index = offset; /* 0 = intr_spi 0 */
rmIrqReq.dst_id = dest_dev; /* TISCI_DEV_MCU_R5FSS0_CORE0 */
rmIrqReq.dst_host_irq = intNum; /* 213 = OUTL_53 mapped IRQ */
rmIrqReq.global_event = 0;
rmIrqReq.ia_id = 0;
rmIrqReq.vint = 0;
rmIrqReq.vint_status_bit_index = 0;
return Sciclient_rmIrqSet(&rmIrqReq, &rmIrqResp, SCICLIENT_SERVICE_WAIT_FOREVER);
}
/* Call: */
intern_CfgIrqRouter(TISCI_DEV_MCSPI5, 0, TISCI_DEV_MCU_R5FSS0_CORE0,
CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_53);
Sciclient_rmIrqSet() returns an error code: -1
My question:
1. Does dst_host_irq = 213 fall within the interrupt allocations for MCU1_0 in the default boardcfg_rm?
2. Is MCSPI5 officially supported as an interrupt source for MCU1_0 in the J721E architecture?