TDA4APE-Q1: TDA4APE6-Q1

Hi,

venkatesan s said:

In the pinmux tool, CPSW9X MDIO1_MDIO / MDIO1_MDC are multiplexed with VOUT0_DATA6 and VOUT0_DATA7 (pins K32 and G32). Since these two VOUT0 signals do not have any alternate pin options, we cannot use MDIO1 without sacrificing the VOUT interface.

What interface from DSS is used here? We have direct DP & DSI controllers available in the SOC, allowing you to output DP & DSI signals for the Display.

When you want to use DPI signals directly from DSS, then you might need to use VOUT0_DATA6 and VOUT0_DATA7 (pins K32 and G32).

venkatesan s said:

Can we use MDIO0 as a shared MDIO bus for both CPSW2G and CPSW9X PHYs? In other words, is it valid to route both Ethernet interfaces to the same MDIO0_MDC/MDIO0_MDIO pins and manage all PHYs from a single MDIO controller?

Ideally possible, but not validated at the TI side.
Essentially, you need to enable both CPSW instances and link to the same MDIO nodes if using Linux. It is flexible when using both CPSW instances, CPSW2G and CPSW9x, from the same core.

Best Regards,
Sudheer

Hi Sudheer,

We are developing a custom board for the AI Analytics card using the TDA4APE6-Q1 SoC and require three video outputs from the board:

1. MIPI LCD display — supported directly by the SoC, no issues expected.

2. HDMI port — we want to convert 24-bit RGB from the SoC to HDMI using DSS0 signals.

3. VGA port — we need a solution to provide a VGA (analog) output; source is currently MIPI.

Could you please advise which approach is the easiest and requires the fewest components for implementing the HDMI and VGA outputs from the SoC

Hi,

venkatesan s said:

We are developing a custom board for the AI Analytics card using the TDA4APE6-Q1 SoC and require three video outputs from the board:

Understood, you are planning to use 3 video outputs from the SoC.

venkatesan s said:

Could you please advise which approach is the easiest and requires the fewest components for implementing the HDMI and VGA outputs from the SoC

Let me loop in our display expert to assist you further.

Best Regards,
Sudheer

Hi Venkatesan,

For HDMI, the AM69 SK board's DTS can be used as reference for software connectivity: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm64/boot/dts/ti/k3-am69-sk.dts?h=ti-linux-6.12.y#n288.

And the AM69 SK board's schematic files can be used for reference for the hardware connectivity: https://www.ti.com/lit/zip/SPRR466 

AM69 is the industrial variant of TDA4AP, and TDA4APE is the cut down version of TDA4AP. So, DSS IP should be the same between AM69 and TDA4APE.

For VGA, we do not have any reference boards or software. But general idea should be the same as HDMI (aka, a bridge that converts DSI or DPI to VGA).

Regards,

Takuma

Dear Sudheer,

Also we wanted to use 

1.SERDES1 Lane0 (Gen3 x1) → to PCIe-to-SATA bridge IC (dual SATA drives)

2.SERDES1 Lane1(Gen3 x1)→ as USB 3.0 HUB

Each SERDES1 lane can be configured independently???so one lane can run PCIe Gen2 x1 and the other USB3.0 DRD???

Hi,

SerDes can support a maximum of two functionalities, such as PCIe + SGMII or PCIe + USB or USB + SGMII, and so on.

When you want to use it for PCIe + USB, then you can't use the same SerDes for any other functionalities.

Best Regards,
Sudheer

Hi,

To understand more clearly i have done block diagram .Kindly confirm this can be done