AM67A: Enable 3 screens with LVDS-1 LVDS-2 and DSI-0

Part Number: AM67A

Hi,

Previously I configured my device tree to enable three screens using LVDS single lanes LVDS-1 and LVDS-2 and DSI-0. I have video output for LVDS-1 and DSI-0. However, I've found on SDK11 that I am still unable to get a clock signal on LVDS-2 with this setup. I followed the guide and have applied the patch which removes the companion-panel.

When I intentionally configure the companion panel, I get duplicate output on the LVDS-2 screen, but without companion panel it does not output anything, the peripheral is disabled.

cat /sys/kernel/debug/clk/clk_summary | grep dss
 clk:232:8                           1       1        0        320000000   0          0     50000      Y   30220000.dss                    fck
    clk:232:4                        1       1        0        82552000    0          0     50000      Y      30220000.dss                    vp2
       clock-divider-oldi-dss1       1       1        0        87100000    0          0     50000      Y         30220000.dss                    vp1
 clk:186:6                           1       1        0        320000000   0          0     50000      Y   30200000.dss                    fck
    clk:186:2                        0       0        0        300000000   0          0     50000      Y      30200000.dss                    vp2
    clock-divider-oldi-dss0          1       1        0        87100000    0          0     50000      Y      30200000.dss                    vp1

Notice oldi-dss1 on vp1. This clock is configured correctly, and says it's enabled, but the pin is not actually toggling.

Could someone help me debug why the peripheral is not output despite appearing correctly in kmsprint and the clk_summary?

kmsprint --device /dev/dri/card2
Connector 0 (41) LVDS-2 (connected)
  Encoder 0 (40) NONE
    Crtc 0 (39) 1920x720@56.36 87.100 1920/53/54/53/? 720/8/7/8/? 56 (56.36) P|D
      Plane 0 (32) fb-id: 55 (crtcs: 0 1) 0,0 1920x720 -> 0,0 1920x720 (AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 XR15 XB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12)
        FB 55 1920x720 XR24
Connector 1 (52) DSI-1 (connected)
  Encoder 1 (51) NONE
    Crtc 1 (50) 1280x800@64.01 82.550 1280/100/32/100/- 800/20/3/30/- 64 (64.01) P|D
      Plane 1 (43) fb-id: 58 (crtcs: 0 1) 0,0 1280x800 -> 0,0 1280x800 (AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 XR15 XB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12)
        FB 58 1280x800 XR24

Here are the important parts of the device tree:

...
	panel0 {
		compatible = "dlc,dlc1010gig";
		rotation = <180>;
		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				lcd_in0: endpoint {
					remote-endpoint = <&oldi0_dss0_out>;
				};
			};
		};
	};

	panel1 {
		compatible = "dlc,dlc1010gig";
		rotation = <180>;
		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				lcd_in1: endpoint {
					remote-endpoint = <&oldi1_dss1_out>;
				};
			};
		};
	};
...

&dss0 {
	status = "okay";
};

&dss0_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	/* VP1: LVDS Output (OLDI TX 0) */
	port@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		dss0_dpi0_out0: endpoint@0 {
			reg = <0>;
			remote-endpoint = <&oldi0_dss0_in>;
		};
	};

};

&oldi0_dss0 {
	status = "okay";
};

&oldi0_dss0_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
		reg = <0>;

		oldi0_dss0_in: endpoint {
			remote-endpoint = <&dss0_dpi0_out0>;
		};
	};

	port@1 {
		reg = <1>;

		oldi0_dss0_out: endpoint {
			remote-endpoint = <&lcd_in0>;
		};
	};
};

&oldi1_dss0 {
	status = "disabled";
};

&dss1 {
    status = "okay";

    clocks = <&k3_clks 232 8>,
            <&dss1_vp1_clk>,
            <&k3_clks 232 4>;

    clock-names = "fck", "vp1", "vp2";

    assigned-clocks = <&k3_clks 235 7>, /* DEV_OLDI_TX_CORE1_OLDI_PLL_CLK */
            <&k3_clks 241 0>,    /* DSS1-VP0 */
            <&k3_clks 240 0>;    /* DSS1-VP1 */

    assigned-clock-parents = <&k3_clks 235 9>, /* DEV_OLDI_TX_CORE1_OLDI_PLL_CLK_PARENT_HSDIV0_16FFT_MAIN_18_HSDIVOUT0_CLK */
            <&k3_clks 241 1>,    /* PLL 18 OLDI */
            <&k3_clks 240 2>;    /* PLL 17 DSI */
};

&dss1_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	/* VP0: LVDS Output (OLDI TX 1) */
	port@0 {
		reg = <0>;
		status = "okay";

		dss1_dpi0_out: endpoint {
			status = "okay";
			remote-endpoint = <&oldi1_dss1_in>;
		};
	};

	/* DSS1-VP1: DSI Output */
	port@1 {
		reg = <1>;

		dss1_dpi1_out: endpoint {
			remote-endpoint = <&dsi0_in>;
		};
	};
};

&oldi1_dss1 {
	status = "okay";
};

&oldi1_dss1_ports {
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
		reg = <0>;
		status = "okay";

		oldi1_dss1_in: endpoint {
			status = "okay";
			remote-endpoint = <&dss1_dpi0_out>;
		};
	};

	port@1 {
		reg = <1>;
		status = "okay";

		oldi1_dss1_out: endpoint {
			status = "okay";
			remote-endpoint = <&lcd_in1>;
		};
	};
};

&dphy_tx0 {
	status = "okay";
};