Hi
The link below explains why the SRIO RapidIO ENTX bit is not set for the C6474. I'm using C6472 so the reason why its not set should be the same.
http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/t/11503.aspx
"The reason that you read the ENTX bit as zero is that it is controlled by SRIO low level hardware state machines, as well as the SERDES_CFGTXn_CNTL MMR bit. Essentially the MMR bit output is ANDed with the HW control function and this signal is fed to the Serdes registers. So when you read this bit, it is also indicating the ANDed signal. "
However, the "MMR bit", refers to the CFGTXn_CNTL ENTX bit right?
Are there any bits that tell me which of the SRIO low level tx hardware state machines are not happy?
We also have an issue with the PORT_OK bit = 0 yet the PORT_INITIALIZED bit = 0. I suspect this is due to an Rx problem so I found the SERDES_CFGRXn_CNTL bit LOS (loss of signal) that I thought would help. But the problem is, once this is enabled, how can I determine if the threshold has violated?
Basically, what I'm looking for is some type of indicator that the signal level isn't what it should be. We're trying to determine if we have a BGA soldering issue.
Cheers
Eddie