AM6442: Locks MCU PLL boot

Thomas Mongellaz

Part Number: AM6442
Other Parts Discussed in Thread: SYSCONFIG

Hi expert,

I have a question regarding the boot process and the locking of the PLLs during boot.

In the 'Boot Process Flow', there is a step called 'DMSC ROM Configures PLLCTRL and Locks MCU PLL'.

Does this step configure the MCU PLL, and then wait for the PLL to lock, or does the program proceed to the next step even if the PLL is not locked ?

In the datasheet and in the TRM, I couldn’t find any values regarding the minimum and maximum frequencies for the PLLs.

Could you provide the lock range and capture range specifications for the MCU PLL (connected to the external oscillator) on the AM64 MPU ?

Best Regards,

Thomas

3 months ago

0 Stanislav Stilyanov 3 months ago

TI__Mastermind 24070 points

Hi Thomas,

ROM code locks PLLs that are only needed for the selected boot peripherals like USB, SD card, etc.) ROM does not lock PLLs that are not needed for its function.

Regards,

Stan

0 Thomas Mongellaz 3 months ago in reply to Stanislav Stilyanov

Prodigy 140 points

Hi,

thank you for your reply.

I would like to know what is the minimum and maximum admissible input frequency range (FREF) for the PLLs of the AM64 (MCU_PLL0) ?

Best Regards,

thomas

0 Thomas Mongellaz 3 months ago in reply to Stanislav Stilyanov

Prodigy 140 points

Hi,

thank you for your reply.

I would like to know what is the minimum and maximum admissible input frequency range (FREF) for the PLLs of the AM64 (MCU_PLL0) ?

Best Regards,

thomas

0 Stanislav Stilyanov 3 months ago in reply to Thomas Mongellaz

TI__Mastermind 24070 points

Hi Thomas,

You can refer to the Sysconfig tool where you can play with hsdivider values.

https://dev.ti.com/sysconfig/#/config/?args=--product%20%2Fmnt%2Ftirex-content%2Fsitara_ctt_1_1_4%2F.metadata%2Fproduct.json%20--device%20AM6442%20--package%20%22FCBGA%20P$OPEN$ALVP$CLOSE$%22%20--variant%20AM6442-D%20--context%20system

Thanks,

Stan

0 Thomas Mongellaz 3 months ago in reply to Stanislav Stilyanov

Prodigy 140 points

Hi,

I have experimented with the clock configuration, but this does not provide any information about the PLL lock range.

What I can deduce is that the PLL is able to lock with a 12.5 MHz clock (the internal RC oscillator of the AM64, clk_12m_rc), because the outputs of the HSDIV are not equal to fref_clk.(According to what the SysConfig tool shows me.)

What I want to know is, for example, if HSFOS0 has a fault and my crystal oscillates at 10 MHz instead of 25 MHz, will my PLL still lock? I would like to know the input PLL lock range.

best regards,

thomas

0 Stanislav Stilyanov 3 months ago in reply to Thomas Mongellaz

TI__Mastermind 24070 points

Hi Thomas,

The supported external crystal frequency is 25 MHz. 12.5 MHz internal oscillator is a fail-safe oscillator turning on if external clock loss was detected. PLLs will continue to work, however this is an emergency situation that needs to handled accordingly.

Regards,

Stan

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AM6442: Locks MCU PLL boot