• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 97 subscribers
  • Views 381 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM1808 USB number of endpoints

Qmax
Expert 2280 points
Other Parts Discussed in Thread: AM1808

Dear all,

I have some questions about USB 2.0 Controller on AM1808. Both Datasheet and TRM state that it has 4 TX and 4 RX endpoints (plus ep0), 4KB FIFO RAM, and include a DMA controller with 4 TX and 4 RX DMA channels. Looking at code in kernel drivers/usb/musb/musb_core.c file, it seems number of endpoints, their role and related FIFOs are configurable and can be changed, but looking at TI documents I doubt USB HW Controller can support a different configuration.

So my question is: can AM1808 USB 2.0 Controller be configured in a different way that 4RX+4TX eps?
Can I have more that 8 eps, or 8 eps with different roles (eg. 3 TX + 5 RX)?

Currently the following configuration is used:

/* mode 2 - fits in 4KB */
static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = {
{ .hw_ep_num = 1, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num = 1, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num = 2, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num = 2, .style = FIFO_RX,   .maxpacket = 1024, },
{ .hw_ep_num = 3, .style = FIFO_TX,   .maxpacket = 512, },
{ .hw_ep_num = 3, .style = FIFO_RX,   .maxpacket = 512, },
{ .hw_ep_num = 4, .style = FIFO_TX,   .maxpacket = 256, },
{ .hw_ep_num = 4, .style = FIFO_RX,   .maxpacket = 128, },
};

Is there any specific reason why ep2.RX has maxpacket size to 1024?

Thanks in advance.
Best regards,

Max

  • 0
    TI__Genius 9460 points

    The endpoints will have to be 4Rx and 4Tx. We can change the FIFO sizes of these endpoints but 3Tx + 5Rx is not possible.

    ep2.Rx is 1024 to accomodate usb camera ISO IN endpoint which has epsize as 1024.

    Ajay

  • 0 in reply to Ajay
    Expert 2280 points

    Ajay, thanks very much for you clarification.

    Reading more in details the TRM I've understood that 4+4 eps configuration is related to HW capabilities.

    I have one more question. I'm trying to build and USB composite gadgets. I've tried both the g_cdc (ETH+ACM) and a "reduced version" of g_multi (ETH+MSC without ACM). And both of them cause the kernel to crash with something like:

    Backtrace:
    [<c00ab43c>] (__kmalloc_track_caller+0x0/0xcc) from [<c0277d54>] (__alloc_skb+0x58/0xf0)
     r8:bf061b98 r7:00000820 r6:00000020 r5:c30c6480 r4:c3802180
    [<c0277cfc>] (__alloc_skb+0x0/0xf0) from [<bf061b98>] (rx_submit+0xb8/0x1a4 [g_multi])
    [<bf061ae0>] (rx_submit+0x0/0x1a4 [g_multi]) from [<bf06201c>] (rx_complete+0x250/0x258 [g_multi])
    [<bf061dcc>] (rx_complete+0x0/0x258 [g_multi]) from [<c023b40c>] (musb_g_giveback+0x150/0x188)
    [<c023b2bc>] (musb_g_giveback+0x0/0x188) from [<c023c43c>] (musb_g_rx+0x228/0x290)

    That seems something related to u_ether.c code called from musb code.

    I have no issue with simple g_ether, so I wonder if I am missing some specific configuration.

    Thanks for your support. Regards,

    Max