Hello,
On the evaluation board, DDR3 memory is 64 bits consists of 4 chips 512 x 16 bits (+ 1 reserve for ECC). We consider in some cases only two chips to reduce consumption.
I have to identify the change in the configuration register DDR_SDCFG, toggling the NM bit from 0 to 1.
Is this the only change necessary?
By doing this, we expect an increase in access time DDR3: is this really the case?
For now, the first tests suggest otherwise and we're surprised, please advise
