AUDIO-AM275-EVM: UDMA circular addressing

Hello Satoshi Tomimatsu,

Circular buffer mode is mainly used when there is a continuous stream of data coming from a peripheral or module, and we must avoid any data loss while maintaining real-time performance.

In this mode, the DMA is configured with two buffers (Ping-Pong buffers). The DMA will keep writing data alternatively to these two buffers in a circular sequence.

How it works:
1. DMA starts writing into Buffer-A
2. When Buffer-A becomes full → Interrupt #1 is triggered
Meanwhile DMA automatically switches to Buffer-B
3. When Buffer-B becomes full → Interrupt #2 is triggered
Meanwhile DMA switches back to Buffer-A
4. The process continues circularly without stopping

On AM275x, this behavior can be achieved by using a Type-15 TR configuration where we can generate interrupts when:
• Half of the transfer is complete
• Full transfer is complete

This ensures continuous data flow with real-time processing capability.

Additional Info Required :

To provide the best solution and configuration example, we request the following details:
• Which peripheral or source generates the data?
• Required buffer size?

Once we receive the above information, we will share configuration example for your exact use case.

Regards,

Anil.

Hello Swargam Anil,

I was not referring to ping-pong buffers or double-buffering.
What I am looking for is a circular addressing scheme, where the effective address automatically wraps around after reaching the buffer size.

In other words:

effective_address = base + (offset % buffer_size)

This is commonly used for FIR delay lines or ring buffers, where the DMA continues reading/writing in a circular manner within a single buffer.

Is such circular addressing supported by the AM275x UDMA?
If so, how can it be configured?

Thank you.

Hello Satoshi Tomimatsu,

In my view, if we load the Transfer Request (TR) an infinite number of times, then upon every completion of the DMA transfer, the DMA starts freshly from the starting address and continues the operation until the end address is reached. Once that specific DMA block transfer is done, the user (software) receives a notification (interrupt), and then, without any software intervention, the TR is reloaded infinitely by the hardware. The user gets interrupts continuously. Is this the behavior you are expecting? Based on the requirements, the above method should work for your use case. Please let me know if I have misunderstood the use case in a different way. If the above explanation is not working for you, please explain the full details about your specific use case and provide an example.

Regards,

Anil.

Hello, Swargam Anil

I will be a bit more specific about my question.

Basically what I wanted to do is to create a large delay line / ring buffer on HyperRAM (for example, 1 MB).
However, since direct access to HyperRAM is too slow, I keep a small view (for example, 64 bytes) of the data in SRAM to work with. 
Data transfer between SRAM and HyperRAM is done with UDMA. 

The method you suggested works only when the offset of the view is aligned to the view size (i.e. multiples of 64 bytes).
In my usecase, the offset can be any arbitrary number of bytes.
Therefore upon reaching the delay line limit of 1 MB, TR has to be split in two: one for the end of the buffer and one for the beginning.
If circular addressing feature were available, it can be handled in single TR. 

Please let me know if such feature is available in AM275 processor.

Thank you,

Satoshi Tomimatsu