Other Parts Discussed in Thread: AM69
Following on from:
Appologies for the delayed response, back looking at this now.
I can now see the patches you refer to have been included in newer kernels and the AM69 can now support devices which require large 32bit non-prefetchable BARs (nearly upto 4GB):
ranges = <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
<0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
This is great, but what about devices with 64bit pre-fetchable BARs ?
If I was to split this address region up into 3 regions:
I/O 1MB
32bit Non-prefetch 2GB - 1MB - 4KB
64bit Pre-fetch 2GB
Would the hardware support this ?
I think the Cadence IP and Upstream linux driver should support this, and I can see a more standard setup in another SoC which uses the Cadence IP (but not a Ti Part) the "sophgo,sg2044" here is its 'ranges' entry from the PCIe node of its device tree:
ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00200000>, /* IO */ <0x42000000 0x0 0x10000000 0x0 0x10000000 0x0 0x04000000>, /* 32bit Prefetchable */ <0x02000000 0x0 0x14000000 0x0 0x14000000 0x0 0x04000000>, /* 32bit */ <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, /* 64bit */ <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; /* 64bit Prefetchable */
All bases are covered, so all devices should enumerate if they can fit in the sizes allocated.
