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AM6421: OSPI interface timing parameter concern

Vincent Wang
Prodigy 130 points

Part Number: AM6421

Hello experts,

We are working on the OSPI communication design with FPGA. We found the below parameters. One parameter O12 is big range (MIN: -4.25, MAX: 7.25). Why does the delay time have big range?

Screenshot 2025-12-12 103559.jpg

OSPI is working on 50MHz, SDR mode.

The cycle of OSPI is 20ns, but the delay time O12 is more than 10ns.

Could you help to check why the tolerance is so large?

 

  • 0
    TI__Mastermind 23060 points

    Hi Vincent,

    • O9 is slightly less than 10 ns
    • O8 is slightly less than 10 ns
    • O12 is MAX 7.25 ns  after clock falling edge, which is less than 10 ns
    • O12 is MAX 4.25 ns  before clock falling edge, which is less than 10 ns

    My understanding is that data is read on rising edge, so that should be fine

    I cannot comment for the exact figures, but they seem plausible.

    Regards,

    Stan