TDA4VM: [J721E][TDA4VM][AUDIO][MCASP][UDMA]The issue of audio channel data offset

Hi bean lai,

Can you share your code that you are using to set up the MCASP?

Best,
Jared

Hi bean lai,

TRM about buffer overrun:

A buffer overrun occurs when a serializer is instructed to transfer data from XRSRn shift register to XRBUFn
receiver buffer, but the corresponding MCASP_RBUFn register has not yet been read since the last time the
transfer occured. When this occurs, the receiver state machine sets the overrun flag - ROVRN. However, the
individual serializer writes over the data in the XRBUFn buffer register (destroying the previous sample) and
continues shifting (n = 0 to 15).

An overrun is checked only once per time slot. The MCASP_RSTAT[0] ROVRN flag is set when an overrun
condition occurs. It is possible that an overrun occurs on one time slot but then the host catches up and does not
cause an overrun on the following time slots. However, once the ROVRN flag is set, it remains set until the host
explicitly writes a 1 to the ROVRN bit to clear the ROVRN bit.

Do your settings line up with the speed of the data coming from the upper computer?

Best,
Jared

Yes, the clock signal of the upper computer is provided by the TDA4VM side.

Hi bean lai,

Is there something else running on the C6 that could stall the MCASP from clearing the FIFO in time?

Best,
Jared

We use C6x_2 to handle the audio process alone, while the other processes run on other cores and use UDMA for handling.Indeed, this issue occurs when all peripherals are connected, such as CMOS and screens. However, it is fine if there is only audio

BR

My main question is whether there are any areas in mcasp & udma that can be optimized without modifying other processes.

BR

Is this related to the FIFO threshold setting in mcasp or the UDMA ring buffer setting? No matter how I adjust them, the ROWRN problem still occurs.

BR

Hi bean lai,

bean lai said:

Indeed, this issue occurs when all peripherals are connected, such as CMOS and screens. However, it is fine if there is only audio

My guess is there is some stall from DDR usage due to the screens. Can you test whether there is a specific peripheral that is causing the issue?

bean lai said:

Is this related to the FIFO threshold setting in mcasp or the UDMA ring buffer setting? No matter how I adjust them, the ROWRN problem still occurs.

Increasing the FIFO size wouldn't hurt, but I assume it's an issue with transactions being stalled due to higher priority requests taking precedence.

You can try QoS settings:  [FAQ] TDA4VH-Q1: How do I control the quality of service (QoS) and class of service (CoS) settings on TDA4 devices to balance transaction loads and priorities?  

Best,
Jared

I also suspect that it's an issue with transactions being stalled due to higher priority requests taking precedence.

The udma priority of the audio has been adjusted to the highest.

Hi bean lai,

Jared McArthur said:

You can try QoS settings:  [FAQ] TDA4VH-Q1: How do I control the quality of service (QoS) and class of service (CoS) settings on TDA4 devices to balance transaction loads and priorities?  

Can you try following the instructions in the FAQ to see if the transactions are truly running at the highest priority?

Jared McArthur said:

Can you test whether there is a specific peripheral that is causing the issue?

Can you also do the above?

Best,
Jared

Jared McArthur said:

Can you test whether there is a specific peripheral that is causing the issue?

Can you also do the above?

[beanlai]: This has been tested; plugging in a CMS camera increases the probability of recurrence.

You can try QoS settings:  [FAQ] TDA4VH-Q1: How do I control the quality of service (QoS) and class of service (CoS) settings on TDA4 devices to balance transaction loads and priorities?  

Can you try following the instructions in the FAQ to see if the transactions are truly running at the highest priority?

[benalai]: The FAQ is a bit long; I need to understand it. Or could you provide more intuitive suggestions for me to try?

Hi bean lai,

bean lai said:

[beanlai]: This has been tested; plugging in a CMS camera increases the probability of recurrence.

Does this include display usage?

bean lai said:

[benalai]: The FAQ is a bit long; I need to understand it. Or could you provide more intuitive suggestions for me to try?

I do not have anything more intuitive for QoS settings. You could try editing the resource management and increasing the DMA rings allocated to the C6x (https://dev.ti.com/sysconfig/#/start).

Best,
Jared

When I allocate memory for the buffer, there are several types available. I'm currently using APP_MEM_HEAP_DDR_SCRATCH, but I want to use other types, which is not working. How should I configure it to allocate other memory types, such as dedicated hard drives without cache?

Below are the states of several memory types：

[C6x_2 ] 400.851289 s: [mcaspIsrMemAlloc 1318]->isr rx - tx addr 0x0 - 0x0 bytes 24576
[C6x_2 ] 400.851308 s: [mcaspIsrMemAlloc 1329]->id - name - total - free 0 - DDR_LOCAL_MEM - 0x1000000 - 0xfff100
[C6x_2 ] 400.851325 s: [mcaspIsrMemAlloc 1329]->id - name - total - free 1 - INVALID - 0x0 - 0x0
[C6x_2 ] 400.851340 s: [mcaspIsrMemAlloc 1329]->id - name - total - free 2 - L2_MEM - 0x38000 - 0x38000
[C6x_2 ] 400.851355 s: [mcaspIsrMemAlloc 1329]->id - name - total - free 3 - INVALID - 0x0 - 0x0
[C6x_2 ] 400.851370 s: [mcaspIsrMemAlloc 1329]->id - name - total - free 4 - DDR_SCRATCH_MEM - 0x3000000 - 0x3000000
[C6x_2 ] 400.851386 s: [mcaspIsrMemAlloc 1329]->id - name - total - free 5 - INVALID - 0x0 - 0x0
[C6x_2 ] 400.851401 s: [mcaspIsrMemAlloc 1329]->id - name - total - free 6 - INVALID - 0x0 - 0x0
[C6x_2 ] 400.851415 s: [mcaspIsrMemAlloc 1329]->id - name - total - free 7 - INVALID - 0x0 - 0x0
[C6x_2 ] 400.851430 s: [mcaspIsrMemAlloc 1333][E]-->mcasp->rxIsrAddr != 0 failure

Hi bean lai,

There is not a setting to allocate other memory types like eMMC, PCIE, etc.

Best,
Jared

Hi Jared，

The ROWRN error is not occurring, but the XDMAERR error is occurring when data is being sent from another mcasp port.

The configuration of the mCASP transmit port differs slightly from that of the receive port.

Hi bean lai,

What does the code snippet that you've sent relate to?

What exactly is your setup? Are you testing a new McASP port to transmit data for the C6x?

Best,
Jared

Hi Jared McArthur，

We use mcasp4 to capture audio data from the upper computer, and then forward it to the lower computer (amplifier) ​​for playback via mcasp10. Previously, the mcasp4 would encounter a ROVRN error during reception, which has now been resolved. However, a new problem has arisen: during stress testing, the mcasp10 encountered a DMA error during transmission.

Data transmitting and receiving are both triggered by the mcaspSubmitChan function.

Hi Jared McArthur，

Additionally, a DMA ERR also occurred on the link from mcasp10 rx to mcasp4 tx today.

Therefore, DMA err usually occurs on the TX channel of mcasp（both mcasp4 and mcasp10).

Hi bean lai,

bean lai said:

Previously, the mcasp4 would encounter a ROVRN error during reception, which has now been resolved.

How was this resolved?

bean lai said:

However, a new problem has arisen: during stress testing, the mcasp10 encountered a DMA error during transmission.

Do you have an error message or log for this?

Best,
Jared

Hi Jared McArthur，

Jared McArthur said:

Previously, the mcasp4 would encounter a ROVRN error during reception, which has now been resolved.

How was this resolved?

I changed the type of the audio frame memory heap.

Jared McArthur said:

Do you have an error message or log for this?

[C6x_2 ] 11846.779175 s: [ErrorWatchDogRoutine 312]->port AMP
[C6x_2 ] 11846.779210 s: [ErrorWatchDogRoutine 313]->
[C6x_2 ] ******************* Transmit Watch dog stats ****************
[C6x_2 ] 11846.779226 s: [mcaspAnalyzeErrors 242]->
[C6x_2 ] ------------ Error stats --------------
[C6x_2 ] 11846.779239 s: [mcaspAnalyzeErrors 243]->***** isClkFailErr : 0
[C6x_2 ] 11846.779252 s: [mcaspAnalyzeErrors 244]->***** isDMAErr : 1
[C6x_2 ] 11846.779264 s: [mcaspAnalyzeErrors 245]->***** isSyncErr : 0
[C6x_2 ] 11846.779276 s: [mcaspAnalyzeErrors 246]->***** retVal : -1
[C6x_2 ] 11846.779289 s: [mcaspAnalyzeErrors 248]->***** isRcvOvrRunOrTxUndRunErr : 0
[C6x_2 ] 11846.779307 s: [mcaspCfgPrint 253]->
[C6x_2 ] ------------ reg value --------------
[C6x_2 ] 11846.779320 s: [mcaspCfgPrint 254]->***** mask: 0xffffffff
[C6x_2 ] 11846.779334 s: [mcaspCfgPrint 255]->***** fmt: 0x80f0
[C6x_2 ] 11846.779347 s: [mcaspCfgPrint 256]->***** frSyncCtl: 0x1002
[C6x_2 ] 11846.779359 s: [mcaspCfgPrint 257]->***** clk.clkSetupClk: 0xa0
[C6x_2 ] 11846.779373 s: [mcaspCfgPrint 258]->***** clk.clkSetupHiClk: 0x8000
[C6x_2 ] 11846.779386 s: [mcaspCfgPrint 259]->***** clk.clkChk: 0x0
[C6x_2 ] 11846.779398 s: [mcaspCfgPrint 260]->***** tdm: 0xffffffff
[C6x_2 ] 11846.779412 s: [mcaspCfgPrint 261]->***** intCtl: 0x3
[C6x_2 ] 11846.779424 s: [mcaspCfgPrint 262]->***** stat: 0x15c
[C6x_2 ] 11846.779436 s: [mcaspCfgPrint 263]->***** evtCtl: 0x0

Hi bean lai,

Are your buffers within L2 memory or external memory? If they are in external memory, can you move them to L2?

How are you stress testing the McASP?

Best,
Jared

Jared McArthur said:

How are you stress testing the McASP?

We just keep the system running normally and playing music occasionally.

Jared McArthur said:

Are your buffers within L2 memory or external memory? If they are in external memory, can you move them to L2?

Previously, I was using APP_MEM_HEAP_DDR_SCRATCH, but after changing it to APP_MEM_HEAP_DDR, the problem improved. I also tried using L3, but it caused other parts of the system to malfunction.

Jared McArthur said:

Are your buffers within L2 memory or external memory? If they are in external memory, can you move them to L2?

Hi Jared McArthur, 

Is it true that L2 memory cannot be used as a DMA buffer for data transfer? After moving them to L2, the process runs normally without any errors, but there is no audio data. Under the same environment, moving them to C66X_2_LOCAL_HEAP works normally.

Hi bean lai,

You should be able to use L2, but if C66X_2_LOCAL_HEAP works without issue, even when under your stress testing, then that should be fine.

Best,
Jared

Hi Jared McArthur, 

The C66X_2_LOCAL_HEAP function can transfer data normally, but DMA errors still occur occasionally.

However, I  just move them to L2 makes it impossible to receive data from mcasp&dma.

The system is running normally, memory can be allocated normally, and there are no errors, but there is no audio data.

Hi bean lai,

Can you try the C66X_2_SCRATCH?

Best,
Jared

Hi, Jared McArthur

Jared McArthur said:

Can you try the C66X_2_SCRATCH?

We initially used DDR_C66X_2_SCRATCH_SIZE, but after changing it to DDR_HEAP_MEM_SIZE, the probability of the problem occurring decreased. Now we want to use internal memory.

According to my research, L2 memory is invisible to the UDMA engine. Therefore, even if the allocation is successful, UDMA cannot access L2 memory and thus cannot copy data. Is that correct?

Hi bean lai,

bean lai said:

According to my research, L2 memory is invisible to the UDMA engine.

Do you have links to this?

bean lai said:

Is that correct?

The L2 memory is linked within the UDMA unit tests, so it should be accessible.

Are you able to set memory outside of the UDMA engine?

Best,
Jared

Hi， Jared McArthur

Jared McArthur said:

Do you have links to this?

I just checked TRM, and there's no direct bus connection between the C6X_2 L2 and UDMA. The results confirm that the allocated L2 memory cannot move data.

TRM Figure 1-1 Device Block Diagram

Jared McArthur said:

Are you able to set memory outside of the UDMA engine?

I'm allocating it directly within the C6x_2 application. Or do you have any suggestions or examples on how to allocate C6X L2 memory for udma use? I'm currently allocating it directly using appMemAlloc.

Hi bean lai,

bean lai said:

I just checked TRM, and there's no direct bus connection between the C6X_2 L2 and UDMA. The results confirm that the allocated L2 memory cannot move data.

There's a connection through the interconnect.

Are you using your own McASP driver? Can you use the PDK driver?

Best,
Jared

Hi， Jared McArthur,

Sorry, I took leave last week.

We are using TI's PDK MCASP driver. pdk_jacinto_09_02_00_30

Hi bean lai,

Are you able to move to the latest SDK?

Can you try creating the buffers by copying the method used in audioSample_main.c?

Best,
Jared

Hi， Jared McArthur,

I tried allocating memory according to the method used in audioSample_main.c, but there was no improvement. I've now tried allocating memory from MSMC, but there's still no significant improvement.

[C6x_2 ] 2097.707659 s: [ErrorWatchDogRoutine 352]->port AMP
[C6x_2 ] 2097.707709 s: [ErrorWatchDogRoutine 353]->
[C6x_2 ] ******************* Transmit Watch dog stats ****************
[C6x_2 ] 2097.707728 s: [mcaspAnalyzeErrors 282]->
[C6x_2 ] ------------ Error stats --------------
[C6x_2 ] 2097.707745 s: [mcaspAnalyzeErrors 283]->***** isClkFailErr : 0
[C6x_2 ] 2097.707761 s: [mcaspAnalyzeErrors 284]->***** isDMAErr : 1
[C6x_2 ] 2097.707775 s: [mcaspAnalyzeErrors 285]->***** isSyncErr : 0
[C6x_2 ] 2097.707788 s: [mcaspAnalyzeErrors 286]->***** retVal : -1
[C6x_2 ] 2097.707803 s: [mcaspAnalyzeErrors 288]->***** isRcvOvrRunOrTxUndRunErr : 0
[C6x_2 ] 2097.707825 s: [mcaspCfgPrint 293]->
[C6x_2 ] ------------ reg value --------------
[C6x_2 ] 2097.707841 s: [mcaspCfgPrint 294]->***** mask: 0xffffffff
[C6x_2 ] 2097.707856 s: [mcaspCfgPrint 295]->***** fmt: 0x80f0
[C6x_2 ] 2097.707872 s: [mcaspCfgPrint 296]->***** frSyncCtl: 0x1002
[C6x_2 ] 2097.707885 s: [mcaspCfgPrint 297]->***** clk.clkSetupClk: 0xa0
[C6x_2 ] 2097.707901 s: [mcaspCfgPrint 298]->***** clk.clkSetupHiClk: 0x8000
[C6x_2 ] 2097.707916 s: [mcaspCfgPrint 299]->***** clk.clkChk: 0x0
[C6x_2 ] 2097.707931 s: [mcaspCfgPrint 300]->***** tdm: 0xffffffff
[C6x_2 ] 2097.707948 s: [mcaspCfgPrint 301]->***** intCtl: 0x3
[C6x_2 ] 2097.707961 s: [mcaspCfgPrint 302]->***** stat: 0x154
[C6x_2 ] 2097.707976 s: [mcaspCfgPrint 303]->***** evtCtl: 0x0

Do you have any other suggestions?

Hi bean lai,

Can you try increasing the priority of the C66?

Best,
Jared

Hi， Jared McArthur,

How can I increase the priority of C66?

Hi bean lai,

QoS Registers (within the System Interconnect Registers section).

Table 1-10. CBASS0 QoS Registers 7

Best,
Jared