Part Number: J721EXCPXEVM
Other Parts Discussed in Thread: SYSCONFIG, SK-TDA4VM
Dear TI,
The processor am I using is J721e with PSDK RTOS 09 02 00 05. My aim is to write a custom SPI driver for MCU1_0 in RTOS using the main SPI5 in 3 pin mode, because this channel is outpinned on my custom board. Ifollowed the ti/csl/example/mcspi/mcspiMasterSlave/mcspiMasterSlave_spi1_spi2_v1.c code, however using a digital analyzer the signals that I can see are the SPI clock and the Slave enable (this is handled by GPIO). I checked multiple times all the necessary regsiters like MCSPI_MODULCTRL, MCSPI_CHCONF_0, MCSPI_CHSTAT_0, MCSPI_TX_0, MCSPI_RX_0, but I didn't find error.
/* ========================================================================== */
/* Include files */
/* ========================================================================== */
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <ti/csl/csl_mcspi.h>
/**< For pmModule */
#include <ti/drv/sciclient/sciclient.h>
/**< Interrupt configuration */
#include <ti/osal/osal.h>
#include <ti/csl/soc/j721e/src/cslr_soc_defines.h>
#include <ti/drv/sciclient/soc/sysfw/include/j721e/tisci_devices.h>
#include "bsp/uart.h"
#include "bsp/gpio.h"
#include <ti/csl/src/ip/gpio/V0/gpio.h>
#include <ti/drv/spi/src/SPI_osal.h>
#include "bsp/mcspi_ll.h"
#define MCSPI_INITDLY_0 ((uint32_t) \
MCSPI_MODULCTRL_INITDLY_NODELAY << \
MCSPI_MODULCTRL_INITDLY_SHIFT)
#define PAD_SPI5_RX CSL_CTRL_MMR0_CFG0_BASE + PIN_RGMII6_RD1 /**< SPI RX */
#define PAD_SPI5_TX CSL_CTRL_MMR0_CFG0_BASE + PIN_RGMII6_TD1 /**< SPI TX */
#define PAD_SPI5_CLK CSL_CTRL_MMR0_CFG0_BASE + PIN_RGMII6_TXC /**< SPI CLOCK */
Tcht_spi spi ={
.instance = 5,
.baseAddr = CSL_MCSPI5_CFG_BASE,
.intrEnabled = false,
.spiInClk = 50000000U,
.spiOutClk = 10000000U,
.intrNum = CSLR_MAIN2MCU_LVL_INTRTR0_IN_MCSPI5_INTR_SPI_0,
.intrPriority = 4U,
.clkMode = MCSPI_CLK_MODE_0,
.initDelay = MCSPI_INITDLY_0,
.wordLen = MCSPI_WORD_LENGTH(8), /**< Setting the default world length */
.isrFxn = spi_isr_chnl1,
};
/* ========================================================================== */
/* Global Function Declarations */
/* ========================================================================== */
void mcspi_init()
{
uint32_t status;
HW_WR_REG32(PAD_SPI5_TX, 0x00010003U); // SPI5_SCLK
HW_WR_REG32(PAD_SPI5_RX, 0x00010003U); // SPI5_D0
uart_log("SPI Init Start\n");
spi.chNumb = 0;
spi.wordLen = 8U; /**< Setting the default world length */
McSPIReset(spi.baseAddr);
MCSPISysConfigSetup(spi.baseAddr,
MCSPI_CLOCKS_OCP_ON_FUNC_ON,
MCSPI_SIDLEMODE_NO,
MCSPI_WAKEUP_DISABLE,
MCSPI_AUTOIDLE_OFF);
MCSPISingleChModeEnable(spi.baseAddr);
/**< Enable the master mode */
McSPIMasterModeEnable(spi.baseAddr);
/**< Configure the SPI in Master mode - TX and RX mode - 4 data lines */
status = McSPIMasterModeConfig(spi.baseAddr,
MCSPI_SINGLE_CH,
MCSPI_TX_RX_MODE,
MCSPI_DATA_LINE_COMM_MODE_1,
spi[indx].chNumb);
if (0U == status)
{
uart_log("\nCommunication not supported by SPIDAT[5:0]");
}
/**< Initialize the clock for each instance */
McSPIClkConfig(spi.baseAddr,
spi.spiInClk,
spi.spiOutClk,
spi.chNumb,
spi.clkMode);
/**< Set the word length to 8 bits */
McSPIWordLengthSet(spi.baseAddr,
8,//spi.wordLen,
spi.chNumb);
/**< Setting polarity for SPI */
McSPICSPolarityConfig(spi.baseAddr,
(MCSPI_CH0CONF_EPOL_ACTIVELOW <<
MCSPI_CH0CONF_EPOL_SHIFT),
spi.chNumb);
/**< Set the chip select time control */
McSPICSTimeControlSet(spi.baseAddr,
MCSPI_CS_TCS_1PNT5_CLK,
spi.chNumb);
/** \NOTE: This only should be set with the IMUV3 GYRO and ACCEL switched */
status = MCSPIPinDirSet(spi.baseAddr,
MCSPI_TX_RX_MODE,
MCSPI_DATA_LINE_COMM_MODE_1,
spi.chNumb);
/**< Disable SPIEN: 3-pin mode */
HW_WR_FIELD32( spi.baseAddr + MCSPI_MODULCTRL,MCSPI_MODULCTRL_PIN34, 1);
if (0U == status)
{
uart_log("\nCommunication not supported by SPIDAT[1:0]");
}
uart_log("SPI Instance %d initialized with status %d\n", indx, status);
}
uart_log("SPI Init Done\n");
}
void spi_xfer_dma(uintptr_t args)
{
uint32_t base = spi.baseAddr;
uint32_t ch = spi.chNumb;
uint32_t status;
uint32_t r;
static uint8_t tx[3] = { 0xF1, 0xF1, 0xF1 };
uint8_t rx[3] = { 0 };
McSPIChannelEnable(base,ch);
McSPICSAssert(base, ch);
status = McSPIGetChannelConf(base, ch);
uart_log("SPI Channel Configuration before transfer: 0x%08X\n", status);
status = McSPIChannelStatusGet(base, ch);
if (status != 0U)
{
uart_log("SPI Channel Status before transfer: 0x%08X\n", status);
uint32_t rxReg = McSPIReceiveData(base, ch);
uart_log("\nRX register contains: 0x%08X\n", rxReg);
}
GPIOPinWrite_v0(CSL_GPIO0_BASE,TDA4VM_GPIO_PIN_SPI_CS,0U); // GPIO_PIN_LOW == 0x0U
uint32_t regVal = 0;
regVal = HW_RD_REG32( base + MCSPI_SYST);
uart_log("\nMCSPI_SYST reg: 0x%08X", regVal);
regVal = HW_RD_REG32( base + MCSPI_MODULCTRL);
uart_log("\nMODULCTRL reg: 0x%08X", regVal);
McSPITransmitData(base,(uint32_t) 0xAA,ch);
GPIOPinWrite_v0(CSL_GPIO0_BASE,TDA4VM_GPIO_PIN_SPI_CS,1U);
McSPICSDeAssert(base, ch);
McSPIChannelDisable(base,ch);
}Any advice what else should I check?
Regards,
Ner
