Greetings--
To continue on Zheng's topic of last month:
I'm using one x16 DDR2 part with L138-ZWT.
1. The datasheet specifies length mismatches (Tables 5-36,37,38), but my layout tool is "helping" by
equalizing in time units. I've extracted the inner layer tpd rate at 6.8 ps/mm, which appears about right.
Is there an underlying time sync spec to these path match values?
I'd like to be able to verify the layout paths with only 2 conversions rather than 3.
2. Is there an ETA for the new Hawkboard design? After spending weeks trying to do this in 6L, I'm finding 8L
is still no slam-dunk: The 456MHz part needs 5 supplies (S3v3A, S3v3B/C, S1V8, S1V2, and CVDD(1V3) )
... and this doesn't jibe well with DDR2 routing, which might well be possible in 3L, but not by me....
The only references I'm aware of, the 1808EVM and SOM designs, are 12L and 10L, and I'm getting, uh, resistance at that suggestion.
3. The BGA design Wiki has an error (sorry, sort of OT, but it was a little misleading.)
http://processors.wiki.ti.com/index.php/General_hardware_design/BGA_PCB_design
The table for Feature sizes for Standard BGAs shows 20 mil vias with 5/5, and 18 mil vias with 4/4.
.... You cannot put 5/5 routing between 20 mil vias at 0.8mm pitch. You can escape the top layer pads
(first 2 rows ) with 5/5, but not the vias.
Even 18mils is cutting it too close for DRC: you've only got 31.5 mils to work with, for escape routing.
My board vendor was much more willing to do 4/4 with 20/8 vias than other options.
4. Finally, could someone possibly review my DDR2 section design?
Forums and SI-List are littered with tales of designers with decades of experience crashing and burning with DDR2.
As a noob to this level of complexity, I'm sweating getting this right: multiple repeated turns are not an option.
Many thanks in advance, gurus!
