TDA4VH-Q1: Issue when using C7X L2 when booting from Linux

Wissam Makhlouf

Part Number: TDA4VH-Q1

Hello TI,

I'm using J784S4 on SDK 10_01_00_04.

I'm contacting you because I'm facing a problem when using the C7X L2 memory when booting with linux. Indeed I did several tests :

I tried to create a section in L2 and then use a #pragma to run code in L2 :

It appears that linux fails to load the binary of the corresponding remoteproc, and the EVM keeps restarting and cannot boot.

I tried another method, which use to try to load the binary from u-boot by interrumpting the boot. Here are the steps I followed :
- Copied the app in /run/media/BOOT-mmcblk1p1
- Reboot and interrupt u-boot
- fatls mmc 1:1 (check if the file is here)
- load mmc 1:1 0x90000000 app.bin
- rproc init
- rproc list (get the core id where we want to load the binary)
- rproc load <id> 0x90000000 0x${filesize}
- rproc start <id>

The same problem appears at the load step, the EVM keeps restarting :

To be sure that the problem comes only when booting with linux, I tried my code in NO_BOOT mode, which means there is no running linux, and I am able to run the code in L2 :

Also, I noticed that when using L2 for another purpose, for instance to store the section .stack, I cannot use the L2 unless I use the attribute type=NOLOAD in the linker file, knowing that NOLOAD attribute removes the addresses used from this section in the binary :

It appears that there is an issue when trying to load a binary containing L2 usage, and thanks to those tests I expect there is a conflict with A72 core.

It would be great if you can help me on this topic.

Thank you,

Best regards,

Wissam

7 days ago

0 Suman Anna 7 days ago

TI__Guru** 115735 points

Hi Wissam,

Are you trying to load a firmware that has a loadable program segment in the C7x L2 SRAM?

Can you provide the readelf -l output of your C7x firmware?

regards

Suman

0 Wissam Makhlouf 7 days ago in reply to Suman Anna

Prodigy 50 points

Hi Suman,

Thanks for your feedback.

Indeed I am trying to load a firmware that has a loadable program segment in the C7X L2 SRAM, because it is necessary to run code in L2.

Here is the readelf -l output of the C7X firmware :

Fullscreen output_elf.txt Download

Type de fichier ELF est EXEC (fichier exécutable)
Point d'entrée 0xb2200000
Il y a 17 en-têtes de programme, débutant à l'adresse de décalage 10324760

En-têtes de programme :
  Type           Décalage           Adr.virt           Adr.phys.
                 Taille fichier     Taille mémoire      Fanion Alignement
  LOAD           0x0000000000000040 0x00000000648005c0 0x00000000648005c0
                 0x0000000000000340 0x0000000000000340  R E    0x40
  LOAD           0x0000000000001000 0x00000000b2100000 0x00000000b2100000
                 0x0000000000000098 0x0000000000000098  R      0x1000
  LOAD           0x0000000000200000 0x00000000b2200000 0x00000000b2200000
                 0x0000000000000080 0x0000000000000080  R E    0x200000
  LOAD           0x0000000000400000 0x00000000b2400000 0x00000000b2400000
                 0x0000000000000880 0x0000000000000880  R E    0x400000
  LOAD           0x0000000000600000 0x00000000b2600000 0x00000000b2600000
                 0x0000000000000880 0x0000000000000880  R E    0x200000
  LOAD           0x0000000000608000 0x00000000b2800000 0x00000000b2800000
                 0x0000000000000000 0x0000000002ce0ff4  RW     0x8000
  LOAD           0x0000000000608000 0x00000000b54e1000 0x00000000b54e1000
                 0x0000000000000000 0x00000000000c0000  RW     0x400
  LOAD           0x0000000000608000 0x00000000b55a1000 0x00000000b55a1000
                 0x0000000000030d0c 0x0000000000030e2c  RW     0x20
  LOAD           0x0000000000640000 0x00000000b55d8000 0x00000000b55d8000
                 0x0000000000000000 0x0000000000028000  RW     0x8000
  LOAD           0x0000000000800000 0x00000000b5600000 0x00000000b5600000
                 0x00000000000b0100 0x00000000000b0100  R E    0x200000
  LOAD           0x00000000008b0100 0x00000000b56b0100 0x00000000b56b0100
                 0x0000000000000000 0x0000000000021900  RW     0x8
  LOAD           0x00000000008b1000 0x00000000b56d2000 0x00000000b56d2000
                 0x0000000000000000 0x0000000000010008  RW     0x1000
  LOAD           0x00000000008b1000 0x00000000b56e3000 0x00000000b56e3000
                 0x0000000000000000 0x0000000000000008  RW     0x1000
  LOAD           0x00000000008b1000 0x00000000b56e4000 0x00000000b56e4000
                 0x0000000000000000 0x0000000000010008  RW     0x1000
  LOAD           0x00000000008b1000 0x00000000b56f5000 0x00000000b56f5000
                 0x0000000000000000 0x0000000000000008  RW     0x1000
  LOAD           0x00000000008c0000 0x00000000b5700000 0x00000000b5700000
                 0x0000000000000000 0x0000000000020000  RW     0x20000
  LOAD           0x00000000008c0000 0x00000000b5720000 0x00000000b5720000
                 0x0000000000014ca0 0x0000000000014ca0  RW     0x8

 Correspondance section/segment :
  Sections de segment...
   00     l2_code 
   01     .resource_table 
   02     .text:_c_int00_secure 
   03     .vecs 
   04     .secure_vecs 
   05     .bss 
   06     .sysmem .tracebuf 
   07     .data .args .cio 
   08     .bss:taskStackSection 
   09     .text 
   10     ipc_data_buffer 
   11     .data.Mmu_tableArray .data.Mmu_tableArraySlot 
   12     .data.Mmu_level1Table 
   13     .data.Mmu_tableArray_NS .data.Mmu_tableArraySlot_NS 
   14     .data.Mmu_level1Table_NS 
   15     .stack 
   16     .const

Thank you,

Best regards,

Wissam

0 Suman Anna 6 days ago in reply to Wissam Makhlouf

TI__Guru** 115735 points

Hi Wissam,

Wissam Makhlouf said:
Indeed I am trying to load a firmware that has a loadable program segment in the C7X L2 SRAM, because it is necessary to run code in L2.

Thanks for the details.

This is not possible at load-time from either the A72 U-Boot or Kernel (or even from an R5F core). The C7x L2SRAM is part of the C7x sub-system, but it doesn't have a separate power control on TDA4 devices.

The A72 core would need a separate power control typically for loading this internal memory, while requiring the C7x core to still be in reset. The h/w does not support this, so a loadable program segment in C7x L2 SRAM is not supported.

You would have to rely on your C7x firmware to relocate code while booting.

LOAD 0x0000000000000040 0x00000000648005c0 0x00000000648005c0
0x0000000000000340 0x0000000000000340 R E 0x40

Btw, your C7x linker file should be using the C7x local address 0x800000 instead of the SoC bus address of 0x64800000.

This had worked for you in No-Boot mode because you are actually doing a self-loading from the C7x core itself through CCS.

regards

Suman

0 Wissam Makhlouf 3 days ago in reply to Suman Anna

Prodigy 50 points

Hi Suman,

Thanks for your feedback.

Actually I'm trying to load the C7X code in the related L2, which means First C7X code -> First C7X L2.

In the A72 point of view, we don't do anything except specifying the L2 address range in the device tree, and loading the core with remoteproc. Is it correct to proceed like that?

I tried to relocate the code from the C7X linker, using the C7X local address you gave me, and there is the same problem. I replaced the address 0x64800000 by 0x00800000.

Here is the new readelf -l output :

Fullscreen output_elf_800000.txt Download

Type de fichier ELF est EXEC (fichier exécutable)
Point d'entrée 0xb2200000
Il y a 17 en-têtes de programme, débutant à l'adresse de décalage 10324760

En-têtes de programme :
  Type           Décalage           Adr.virt           Adr.phys.
                 Taille fichier     Taille mémoire      Fanion Alignement
  LOAD           0x0000000000000040 0x00000000008005c0 0x00000000008005c0
                 0x0000000000000340 0x0000000000000340  R E    0x40
  LOAD           0x0000000000001000 0x00000000b2100000 0x00000000b2100000
                 0x0000000000000098 0x0000000000000098  R      0x1000
  LOAD           0x0000000000200000 0x00000000b2200000 0x00000000b2200000
                 0x0000000000000080 0x0000000000000080  R E    0x200000
  LOAD           0x0000000000400000 0x00000000b2400000 0x00000000b2400000
                 0x0000000000000880 0x0000000000000880  R E    0x400000
  LOAD           0x0000000000600000 0x00000000b2600000 0x00000000b2600000
                 0x0000000000000880 0x0000000000000880  R E    0x200000
  LOAD           0x0000000000608000 0x00000000b2800000 0x00000000b2800000
                 0x0000000000000000 0x0000000002ce0ff4  RW     0x8000
  LOAD           0x0000000000608000 0x00000000b54e1000 0x00000000b54e1000
                 0x0000000000000000 0x00000000000c0000  RW     0x400
  LOAD           0x0000000000608000 0x00000000b55a1000 0x00000000b55a1000
                 0x0000000000030d0c 0x0000000000030e2c  RW     0x20
  LOAD           0x0000000000640000 0x00000000b55d8000 0x00000000b55d8000
                 0x0000000000000000 0x0000000000028000  RW     0x8000
  LOAD           0x0000000000800000 0x00000000b5600000 0x00000000b5600000
                 0x00000000000b0100 0x00000000000b0100  R E    0x200000
  LOAD           0x00000000008b0100 0x00000000b56b0100 0x00000000b56b0100
                 0x0000000000000000 0x0000000000021900  RW     0x8
  LOAD           0x00000000008b1000 0x00000000b56d2000 0x00000000b56d2000
                 0x0000000000000000 0x0000000000010008  RW     0x1000
  LOAD           0x00000000008b1000 0x00000000b56e3000 0x00000000b56e3000
                 0x0000000000000000 0x0000000000000008  RW     0x1000
  LOAD           0x00000000008b1000 0x00000000b56e4000 0x00000000b56e4000
                 0x0000000000000000 0x0000000000010008  RW     0x1000
  LOAD           0x00000000008b1000 0x00000000b56f5000 0x00000000b56f5000
                 0x0000000000000000 0x0000000000000008  RW     0x1000
  LOAD           0x00000000008c0000 0x00000000b5700000 0x00000000b5700000
                 0x0000000000000000 0x0000000000020000  RW     0x20000
  LOAD           0x00000000008c0000 0x00000000b5720000 0x00000000b5720000
                 0x0000000000014ca0 0x0000000000014ca0  RW     0x8

 Correspondance section/segment :
  Sections de segment...
   00     l2_code 
   01     .resource_table 
   02     .text:_c_int00_secure 
   03     .vecs 
   04     .secure_vecs 
   05     .bss 
   06     .sysmem .tracebuf 
   07     .data .args .cio 
   08     .bss:taskStackSection 
   09     .text 
   10     ipc_data_buffer 
   11     .data.Mmu_tableArray .data.Mmu_tableArraySlot 
   12     .data.Mmu_level1Table 
   13     .data.Mmu_tableArray_NS .data.Mmu_tableArraySlot_NS 
   14     .data.Mmu_level1Table_NS 
   15     .stack 
   16     .const

Best regards,

Wissam

+1 Suman Anna 2 days ago in reply to Wissam Makhlouf

TI__Guru** 115735 points

Hi Wissam,

Wissam Makhlouf said:
Is it correct to proceed like that?

I tried to relocate the code from the C7X linker, using the C7X local address you gave me, and there is the same problem. I replaced the address 0x64800000 by 0x00800000.

This still won't work if you are trying to load the L2SRAM from A72. Loading the L2SRAM from A72 is simply not possible as I mentioned in my previous response.

You essentially need to ensure that your loadable segments do not have any contents in the C7x L2SRAM. This will boot your C7x successfully, and then you can relocate the code from DDR to L2SRAM from the C7x itself.

regards

Suman

0 Wissam Makhlouf 2 days ago in reply to Suman Anna

Prodigy 50 points

Hi Suman,

Thank you, so I need to find another way to use the L2SRAM for my code, because indeed the loadable segment used L2SRAM. I will try to relocate the code from DDR to L2SRAM after the boot.

Thank you,

Best regards,

Wissam

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TDA4VH-Q1: Issue when using C7X L2 when booting from Linux