Part Number: AM6442
Hello,
I’m looking for information about the MSRAM:
- What is the bus width?
- What is the access latency from the A53 and R5F cores?
I’m designing a simple, low-latency protocol to transfer only a few tens of bytes. The R5F will handle transfers in a high-priority interrupt every few microseconds, and a few bytes of status will be written back to the shared buffer. The ordering of write requests is important. Can the interconnect subsystem reorder writes, or can I rely on writes being observed in program order?
Can I use TCM as the shared buffer instead of MSRAM?
Regards,
Peter
