Hi,
I use a TCI6488 DSP. The system configuration is a master controller, one TCI6488 DSP and 3 FPGAs. All these are interconnected through SRIO switch.
DSP has two SRIO ports for communicating with the master controller and FPGAs.
SRIO is the only medium for communication in this system.
We face a issue where suddenly the transfer b/w master controller and DSP is broken. On the master controller side, the status of DSP's SRIO port is returned NOT-OK. Just before this the ACK-IDs seem to be invalid on master controller side. From DSP software we program the SRIO inside main(). Outside main in the application code, we just write to the LSU registers for a direct-IO NREAD/NWRITE operation. We do not reconfigure the port in any situation. The system is up and running fine for long time. But this issue mentioned above happens suddenly.
Now, in DSP code we don't take care of handling ACK-IDs. It is done by the SRIO peripheral.
1) Has someone faced such issue?
2) Is it possible that external masters could cause this situation?
3) Is there a way to detect port failures and reset and recover to normal behaviour?
We are not really sure if the issue is with DSP port or the switch. This happens in a customer LAB without JTAG connectivity as of now, so have not been able to look at SRIO registers as of now.
Any suggestions are welcome...
Regards,
Justin
