Part Number: TDA4VE-Q1
Hi TI experts,
SW:SDK10.1
HW:our custom board
During the SBL (Secondary Boot Loader) startup process, sbl(tiboot3) does not configure the IO pins. Specifically, the U26 pin initially remains at a low level and is then configured to a high level during the mcu-app startup phase. Under normal conditions, the duration of this low-level state on U26 is approximately 500ms, which is sufficient for our peripheral reset sequencing requirements.
However, we have encountered an issue when performing a system reset via the PMIC (TPS6594133ARWERQ1). When we initiate a reset by writing 0x1 to register 0xAB of the TPS6594, the low-level pulse observed on the U26 pin is only about 40ms. This duration appears too brief to ensure a complete and clean power-down reset, potentially leaving some IO or peripheral states inadequately cleared. The 40ms low period seems insufficient to meet the necessary timing requirements for our specific reset sequence.
Could you please provide insights or recommendations on this matter? Specifically, we would like to understand:
- What determines or configures the 40ms low-level duration during a PMIC-initiated reset?
- Are there methods to extend this low-level period on the U26 pin (or similar system reset signals) when triggering a reset through the TPS6594 PMIC to ensure a more robust power-cycle reset?
Best regards,
Xie jc
