Part Number: AM62L
Dear TI Support Team,
We are currently evaluating the AM62L (SR1.1) device on our custom hardware platform and are facing intermittent and inconsistent boot failures from eMMC. We would like to seek your guidance on whether this behavior is a known limitation of the silicon or related to configuration or boot sequencing.
Platform Details
SoC: AM62L (Silicon Revision SR1.1)
Boot Medium: eMMC
Boot Mode: Reduced Pin Count (BOOTMODE)
Software Stack:
U-Boot (TI SDK 11.01.16.13)
Linux (Yocto-based BSP)
Observed Behavior:
Boot behavior is inconsistent across board power on/off cycles.
Below is a representative console log captured during failure:
NOTICE: bl1_plat_arch_setup arch setup
NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.12.0(release):9f56914fa-dirty
NOTICE: BL1: Built : 13:13:15, Nov 27 2025
NOTICE: BL1: dram_class: 11
NOTICE: lpddr4: post start - PI training status=0x27c0a000
NOTICE: bl1_platform_setup DDR init done
NOTICE: k3_bl1_handoff ENTERING WFI - end of bl1
NOTICE: BL31: v2.12.0(release):9f56914fa-dirty
NOTICE: BL31: Built : 13:13:15, Nov 27 2025
NOTICE: SYSFW ABI: 4.0 (firmware rev 0x000b '11.1.12-v11.01.12 (Fancy Rat)')
ERROR: Agent 0 Protocol 0x10 Message 0x7: not supported
U-Boot SPL 2025.01-g69a2476ac276 (Nov 27 2025 - 13:22:39 +0000)
SPL initial stack usage: 1936 bytes
Trying to boot from MMC0
mmc_load_image_raw_sector: mmc block read error
Partition 1 invalid on device 0
spl_register_fat_device: fat register err - -1
spl_load_image_fat: error reading image u-boot.img, err - -1
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Observations:
eMMC boot inconsistency behaviour observed with While doing power/on off.
Issue is reproducible across multiple boards.
Issue is observed only on SR1.1 silicon.
Questions / Clarifications Requested
Is this eMMC boot instability a known issue on AM62L SR1.1?
Are there any documented errata or ROM limitations affecting eMMC boot on SR1.1?
Are there any recommended boot mode, strap, or timing constraints specific to SR1.1?
Is this behavior resolved or improved in later silicon revisions (e.g., SR2.x)?
Are there any PMIC sequencing or power-up timing requirements specific to SR1.1 that could impact eMMC boot reliability?
We would appreciate your guidance on this issue and any recommended work around or best practices.
Since its very urgent and looks like very critical issue, so kinldy help me resolve the issue as soon as possbile.
Thank you for your support.
Thanks and Best regards,
Kumaresan G