AM275

This FAQ describes various steps to optimize the CAN response time when using OSPI NOR boot mode, It is assumed that the CAN application will be running on R5F0-0 core and all the testing is done on am275-evm

Default Boot flow:

- For AM275 FreeRTOS SDK, SBL and Device Manager firmware are combined in to a single freertos application which runs on the WKUP_R5 core.

Stages to first CAN response:

Steps to Optimize the CAN response time:

1. Disable the SBL print:

In sbl_ospi.c file, remove calls to the following functions

• Bootloader_profileAddCore
• Bootloader_profileAddProfilePoint
• Bootloader_profileUpdateAppimageSize
• Bootloader_profileUpdateMediaAndClk
• Bootloader_profilePrintProfileLog

2. Call to App_runCpus API in sbl_ospi.c can be reordered to improve R5F0-0 boot time:

By default in SBL all the appimages are loaded first (using App_loadImages) and then in the end App_runCpus is called to take all CPUs out of reset, this can lead to increase in the CAN response time. To avoid this, App_runCpus should be moved immediately after App_loadImages.

The following patch includes all the changes required in sbl_ospi.c to reduce the SBL timing:https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/optimized_5F00_sbl.patch

3. Enable Time Slicing for r5 freertos kernel:

diff --git a/source/kernel/freertos/config/am275x/r5f/FreeRTOSConfig.h b/source/kernel/freertos/config/am275x/r5f/FreeRTOSConfig.h
index 1158af46..29b36a9a 100644
--- a/source/kernel/freertos/config/am275x/r5f/FreeRTOSConfig.h
+++ b/source/kernel/freertos/config/am275x/r5f/FreeRTOSConfig.h
@@ -95,7 +95,7 @@
 #endif
 #define configQUEUE_REGISTRY_SIZE               (32)
 #define configUSE_QUEUE_SETS                    (0)
-#define configUSE_TIME_SLICING                  (0) /* keep as 0 to get same functionality as SysBIOS6 */
+#define configUSE_TIME_SLICING                  (1) /* keep as 0 to get same functionality as SysBIOS6 */
 #define configUSE_NEWLIB_REENTRANT              (0)
 #define configENABLE_BACKWARD_COMPATIBILITY     (1)
 #define configNUM_THREAD_LOCAL_STORAGE_POINTERS (10)

4. Change the priority of sciserver task:

The priority of Sciserver task is set to a lower value(3) compared to boot thread by default in the SDK, this is done by Sciserver_tirtosInitPrms_Init API in sciserver_init.c file. Due to this any sciclient request from MCAN app running on will not be serviced by Sciserver until the boot thread completes its execution. The following change will increase this task's priority to match the boot thread, this will allow sciserver task and boot task to execute concurrently as the time slicing is enabled now:

diff --git a/source/drivers/device_manager/sciserver/sciserver_init.c b/source/drivers/device_manager/sciserver/sciserver_init.c
index 704ddc5e..b3025b52 100644
--- a/source/drivers/device_manager/sciserver/sciserver_init.c
+++ b/source/drivers/device_manager/sciserver/sciserver_init.c
@@ -83,7 +83,7 @@ int32_t Sciserver_tirtosInitPrms_Init(Sciserver_TirtosCfgPrms_t *pPrms)
     int32_t ret = SystemP_SUCCESS;
     if (pPrms != NULL)
     {
-#if defined (SOC_AM62PX)
+#if defined (SOC_AM62PX)|| defined (SOC_AM275X)
         pPrms->taskPriority[SCISERVER_TASK_USER_LO] = 30U;
         pPrms->taskPriority[SCISERVER_TASK_USER_HI] = 31U;
 #elif defined (SOC_J722S)

5. Remove sciserver get version API call:

This can be done by defining DEBUG_LOG_DISABLE Macro in sciserver_init.c file.

After the above changes are done, you will have to rebuild the libraries: https://software-dl.ti.com/mcu-plus-sdk/esd/AM275X/11_01_00_16/exports/docs/api_guide_am275x/MAKEFILE_BUILD_PAGE.html#autotoc_md106 and you will also have to rebuild the SBL OSPI example.

Test Set-up:

FreeRTOS SDK version: 11_01_00_16

EVM: AUDIO-AM275-EVM

Bootmode Pin settings (OSPI NOR):

#include <drivers/gpio.h>

/* GPIO PIN Macros */
#define CONFIG_GPIO1_BASE_ADDR (CSL_GPIO1_BASE)
#define CONFIG_GPIO1_PIN (17)
#define CONFIG_GPIO1_DIR (GPIO_DIRECTION_OUTPUT)
#define CONFIG_GPIO1_TRIG_TYPE (GPIO_TRIG_TYPE_NONE)
#define CONFIG_GPIO_NUM_INSTANCES (1U)

static Pinmux_PerCfg_t gPinMuxMainCfg[] = {
    /* MCU_GPIO1 pin config MCU_GPIO1_17 -> PIN_SPI0_CLK */
    {
        PIN_SPI0_CLK,
        ( PIN_MODE(7) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
    },
    {PINMUX_END, PINMUX_END}
};

int main()
{

    Pinmux_config(gPinMuxMainCfg, PINMUX_DOMAIN_ID_MAIN); // Configure PinMux
    GPIO_setDirMode(CONFIG_GPIO1_BASE_ADDR, CONFIG_GPIO1_PIN, CONFIG_GPIO1_DIR);    //Set GPIO direction
    GPIO_pinWriteHigh(CONFIG_GPIO1_BASE_ADDR, CONFIG_GPIO1_PIN); // Set GPIO state to HIGH

#include <drivers/pinmux.h>
#include <drivers/gpio.h>

/* GPIO PIN Macros */
#define CONFIG_GPIO1_BASE_ADDR (CSL_GPIO1_BASE)
#define CONFIG_GPIO1_PIN (18)
#define CONFIG_GPIO1_DIR (GPIO_DIRECTION_OUTPUT)
#define CONFIG_GPIO1_TRIG_TYPE (GPIO_TRIG_TYPE_NONE)
#define CONFIG_GPIO_NUM_INSTANCES (1U)

static Pinmux_PerCfg_t gPinMuxMainCfg[] = {
    /* MCU_GPIO1 pin config MCU_GPIO1_18 -> PIN_SPI0_D0 */
    {
        PIN_SPI0_D0,
        ( PIN_MODE(7) | PIN_INPUT_ENABLE | PIN_PULL_DISABLE )
    },
    {PINMUX_END, PINMUX_END}
};
int main()
{

    Pinmux_config(gPinMuxMainCfg, PINMUX_DOMAIN_ID_MAIN); // Configure PinMux
    GPIO_setDirMode(CONFIG_GPIO1_BASE_ADDR, CONFIG_GPIO1_PIN, CONFIG_GPIO1_DIR);    //Set GPIO direction
    GPIO_pinWriteHigh(CONFIG_GPIO1_BASE_ADDR, CONFIG_GPIO1_PIN); // Set GPIO state to HIGH

AM62D

This section describes steps to optimize the CAN response time for AM62D when using OSPI NOR boot mode, The CAN application runs on MCU R5 core and am62d-evm is used for the testing. The basic approach and some of the steps will remain same as what is already discussed for AM275.

Default Boot flow:

- In FreeRTOS SDK for AM62D Stage-2 SBL and the Device manager application are combined as a single appimage that runs on the WKUP R5 core.

Modified Boot flow:

The above bootflow can be modified to start the MCU R5 application during SBL Stage-1, so It can initialize CAN once SBL Stage-2+DM application starts running on WKUP-R5.

Stages to first CAN response:

Steps to Optimize the CAN response time:

1. Start MCU R5 in SBL Stage-1 instead of Stage-2:

As mentioned above the bootflow can be modified to start MCU R5 core in Stage-1 itself instead of starting it later in SBL stage-2. For this calls to App_loadMCUImage and App_runMCUCpu functions have to be moved to Stage-1 from Stage-2, you will also need to move definitions of these function from sbl_stage2_common.c to main.c of SBL Stage-1 application.

2. Disable the SBL print:

You can add this Macro: DEBUG_LOG_DISABLE in both SBL stages to disable the print logs.

The following patch includes all the changes required in SBL Stage-1 and Stage-2 to reduce the SBL timing:https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_SBL_2D00_OSPI_2D00_changes_2D00_for_2D00_early_2D00_CAN.patch

3. Enable Time Slicing for r5 freertos kernel:

diff --git a/source/kernel/freertos/config/am62dx/r5f/FreeRTOSConfig.h b/source/kernel/freertos/config/am62dx/r5f/FreeRTOSConfig.h
index d5e671c2..893c02a9 100644
--- a/source/kernel/freertos/config/am62dx/r5f/FreeRTOSConfig.h
+++ b/source/kernel/freertos/config/am62dx/r5f/FreeRTOSConfig.h
@@ -95,7 +95,7 @@
 #endif
 #define configQUEUE_REGISTRY_SIZE               (32)
 #define configUSE_QUEUE_SETS                    (0)
-#define configUSE_TIME_SLICING                  (0) /* keep as 0 to get same functionality as SysBIOS6 */
+#define configUSE_TIME_SLICING                  (1) /* keep as 0 to get same functionality as SysBIOS6 */
 #define configUSE_NEWLIB_REENTRANT              (0)
 #define configENABLE_BACKWARD_COMPATIBILITY     (1)
 #define configNUM_THREAD_LOCAL_STORAGE_POINTERS (10) /* Minimun requirement for FreeRTOS FATFS to work */

4. Change the priority of sciserver task:

diff --git a/source/drivers/device_manager/sciserver/sciserver_init.c b/source/drivers/device_manager/sciserver/sciserver_init.c
index 704ddc5e..8d890d93 100644
--- a/source/drivers/device_manager/sciserver/sciserver_init.c
+++ b/source/drivers/device_manager/sciserver/sciserver_init.c
@@ -83,7 +83,7 @@ int32_t Sciserver_tirtosInitPrms_Init(Sciserver_TirtosCfgPrms_t *pPrms)
     int32_t ret = SystemP_SUCCESS;
     if (pPrms != NULL)
     {
-#if defined (SOC_AM62PX)
+#if defined (SOC_AM62PX) || defined (SOC_AM62DX)
         pPrms->taskPriority[SCISERVER_TASK_USER_LO] = 30U;
         pPrms->taskPriority[SCISERVER_TASK_USER_HI] = 31U;
 #elif defined (SOC_J722S)

5. Remove sciserver get version API call:

This can be done by defining DEBUG_LOG_DISABLE Macro in sciserver_init.c file.

After the above changes are done, you will have to rebuild the libraries and you will also have to rebuild the SBL OSPI Stage-1 and Stage-2 examples.

Test Set-up:

FreeRTOS SDK version: 11_02_00_17

EVM: AUDIO-AM62D-EVM

Bootmode Pin settings (OSPI NOR):

AM62A

This section describes steps to optimize the CAN response time for AM62A when using OSPI NAND boot mode, The CAN application runs on MCU R5 core and SK-AM62A-LP EVM is used for the testing.

CAN response proposal:

Initialize MCAN module in SBL Stage-1 to avoid any dependency on DM firmware from MCU R5 application.

Stages to first CAN response:

Steps to Optimize the CAN response time:

1. Disable SBL prints.

2. Enable MCAN clock in SBL Stage-1.

Add following code in SBL Stage-1:

 /* To enable MAIN domain MCAN */
 SOC_moduleClockEnable(TISCI_DEV_MCAN0, 1);
 SOC_moduleSetClockFrequency(TISCI_DEV_MCAN0,TISCI_DEV_MCAN0_MCANSS_CCLK_CLK,AM62AX_MCAN_CLOCK_FREQUENCY);

/* To enable MCU domain MCAN*/
SOC_moduleClockEnable(TISCI_DEV_MCU_MCAN0, 1);
SOC_moduleSetClockFrequency(TISCI_DEV_MCU_MCAN0,TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK,AM62AX_MCAN_CLOCK_FREQUENCY);

3. Changes in clock.c to avoid resetting CAN clock when pminit() is called 

Apply following patch to avoid resetting the CAN clock for both MAIN and MCU domain MCAN:

diff --git a/source/drivers/device_manager/rm_pm_hal/rm_pm_hal_src/pm/soc/am62ax/clocks.c b/source/drivers/device_manager/rm_pm_hal/rm_pm_hal_src/pm/
soc/am62ax/clocks.c
index 086b1f05..73712ae5 100644
--- a/source/drivers/device_manager/rm_pm_hal/rm_pm_hal_src/pm/soc/am62ax/clocks.c
+++ b/source/drivers/device_manager/rm_pm_hal/rm_pm_hal_src/pm/soc/am62ax/clocks.c
@@ -3662,7 +3662,7 @@ const struct clk_data soc_clock_data[260] = {
                .drv            = &clk_drv_pll_16fft,
                .freq_idx       = AM62AX_FREQ_VALUE_PLLFRACF2_SSMOD_16FFT_MAIN_0,
                .data           = &clk_data_pllfracf2_ssmod_16fft_main_0.data_pll.data,
-               .flags          = 0,
+               .flags          = CLK_DATA_FLAG_NO_HW_REINIT,
        },
        [CLK_AM62AX_PLLFRACF2_SSMOD_16FFT_MAIN_0_FOUTPOSTDIV_CLK] =                             {
                .parent =                                                                       {
@@ -3782,7 +3782,7 @@ const struct clk_data soc_clock_data[260] = {
                .drv            = &clk_drv_pll_16fft,
                .freq_idx       = AM62AX_FREQ_VALUE_PLLFRACF2_SSMOD_16FFT_MCU_0,
                .data           = &clk_data_pllfracf2_ssmod_16fft_mcu_0.data_pll.data,
-               .flags          = 0,
+               .flags          = CLK_DATA_FLAG_NO_HW_REINIT,
        },
        [CLK_AM62AX_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK] =                                      {
                .parent =                                                                       {
@@ -4264,7 +4264,7 @@ const struct clk_data soc_clock_data[260] = {
                        1,
                },
                .drv    = &clk_drv_div_pll_16fft_hsdiv.drv,
-               .flags  = 0,
+               .flags  = CLK_DATA_FLAG_NO_HW_REINIT,
                .type   = CLK_TYPE_DIV,
                .data   = &clk_data_hsdiv4_16fft_main_0_hsdiv4.data_div.data,
        },
@@ -4374,7 +4374,7 @@ const struct clk_data soc_clock_data[260] = {
                        1,
                },
                .drv    = &clk_drv_div_pll_16fft_hsdiv.drv,
-               .flags  = 0,
+               .flags  = CLK_DATA_FLAG_NO_HW_REINIT,
                .type   = CLK_TYPE_DIV,
                .data   = &clk_data_hsdiv4_16fft_mcu_0_hsdiv4.data_div.data,
        },

4. Call to App_runCpus API in main.c of SBL S1 can be reordered to improve R5F0-0 boot time:

App_runCpus should be moved immediately after App_loadImages API.

5. Remove SCI Server call from the image running on MCU R5 for MCAN

Use modified System init:

diff --git a/examples/drivers/mcan/mcan_loopback_interrupt/am62ax-sk/mcu-r5fss0-0_freertos/main.c b/examples/drivers/mcan/mcan_loopback_interrupt/am62ax-sk/mcu-r5fss0-0_freertos/main.c
index 126b1737..a4623dea 100644
--- a/examples/drivers/mcan/mcan_loopback_interrupt/am62ax-sk/mcu-r5fss0-0_freertos/main.c
+++ b/examples/drivers/mcan/mcan_loopback_interrupt/am62ax-sk/mcu-r5fss0-0_freertos/main.c
@@ -69,11 +69,20 @@ void freertos_main(void *args)
     vTaskDelete(NULL);
 }
 
+void modSysInit(){
+    /* DPL init sets up address transalation unit, on some CPUs this is needed
+     * to access SCICLIENT services, hence this needs to happen first
+     */
+    Dpl_init();
+    /* Now we can do pinmux */
+    Pinmux_init();
+}
+
 
 int main()
 {
     /* init SOC specific modules */
-    System_init();
+    modSysInit();
     Board_init();
 
     /* This task is created at highest priority, it should create more tasks and then delete itself */

Please note here any API call that might need SCI server services from system_init is removes, so CycleCounterP_init as well as Drivers_uartInit is also removed. If customer doesn't utilize CycleCounterP then it should be fine to remove it, UART has been removed as well, if UART or any other module is required in the MCU application then it also needs to be initialized in SBL for this.

After the above changes are done, you will have to rebuild the libraries, SBL and other applications.

Test Set-up:

MCU+SDK version: 11_01_00_16

EVM: SK-AM62A-LP

Bootmode Pin settings (OSPI NAND):