AM2732-Q1: Callback interrupt problem when using RCSS_SPIA as slave

Hi Ming,

I think this fixed my problem. I have one last question though.

I changed the ending of my spi_slave() function to this:

    while(1){
    transferOK = MIBSPI_transfer(gMibspiHandle[CONFIG_MIBSPI0], &spiTransaction);
    if((SystemP_SUCCESS != transferOK))
    {
        DebugP_assert(FALSE); /* MIBSPI transfer failed!! */
    }
    else
    {
        //DebugP_log("All tests have passed!!\r\n");
    }

    ulEventsToProcess = ulTaskNotifyTake( pdFALSE, portMAX_DELAY );
    if (ulEventsToProcess > 1){
            ;
        }
    }

// uint32_t startCycles;
uint64_t curTime;
float durationCallback[100];

void Spi_Callback(MIBSPI_Handle handle, MIBSPI_Transaction *transaction)
{
    if(intr_callback_cnt>0){
        durationCallback[(intr_callback_cnt-1)%100] = ClockP_getTimeUsec() - curTime;
        // durationCallback[(intr_callback_cnt-1)%100] = (CycleCounterP_getCount32() - startCycles - 15)*1000/400E6;
    }

    // startCycles = CycleCounterP_getCount32();
    curTime = ClockP_getTimeUsec();

    CacheP_wbInv(gMibspiRxBuffer, sizeof(gMibspiRxBuffer), CacheP_TYPE_ALLD);
    intr_callback_cnt++;
    BaseType_t TaskWoken = pdFALSE;
    vTaskNotifyGiveFromISR( gSPI_slave_Task, &TaskWoken );
    portYIELD_FROM_ISR( TaskWoken );
}

My problem now has to do with the time measurement.

When I use ClockP_getTimeUsec(), I accurately measure the 10ms duration from one interrupt to another. When I use the CycleCounterP_getCount32() I always get around 78usec. Why is that huge difference between these 2 time measurement ways.

Thank you in advance.

Dimitra

Hi Ming,

Thank you for the information. I would like to ask for your help with another issue.

I managed to get data from the FPGA. The FPGA sends a 16bit counter every 10us and what I do is modifying my code so that I get 256 packets of 16bit data and after the run I observe the content of the receiving buffer (gMibspiRxBuffer) in memory and I see that all the data is correct.

The problem is that when the FPGA is sending 1024 packets every 10us , I get the data in the receiving buffer correctly but the first 5 packets are zero and the correct counter value starts from the 6th packet. 

Do you know why that happens? I must also mention that in packet numbers over 1024, the same problem appears.

Thank you in advance.

Dimitra

Hi Dimitra,

Since the AM273x is the SPI slave, I would think the issue is on the FPGA side which is the SPI master. 

If you can connect the Saleae Logic Pro to the MIBSPI CS, CLK, MISO, MOSI, you should be able to get the log of the data sent by FPGA. If it matches with the RX buffer contents, then the issue is with the FPGA for sure.

Best regards,

Ming 

Hi Ming,

I confirmed  that the data provided from the FPGA are correct. So the problem lies elsewhere.

My receiving buffer is shown in the picture below when I receive 1024 packets every 10us. It is clearly shown that the first packets of the counter are not received with the right values, although the FPGA sends them correctly (that is verified). The rest of the packets (not the entire buffer is shown in this screenshot) are received correctly.

Do you have an idea why that happens?

Kind regards,

Dimitra

Hi Dimitra,

" although the FPGA sends them correctly (that is verified)"

The verification you mentioned above is on the FPGA side or on the SPI bus connecting the FPGA and AM273x?

From the screen capture of the gMibspiRxBuffer, it only says the AM273x received 6 empty packets, but what is the actual signal sending on the SPI bus is the key. The bottom line is AM273x is a SPI slave, it only gets what the SPI master (FPGA) sent. 

If you can prove the SPI bus does have the first 6 packets with valid data, but AM273x get empty data, then the issue is on the AM273x side.

If the first 6 packet are empty on the SPI bus, then the issue is on the FPGA.

Please capture the SPI bus signals (CS, CLK, MOSI) using Saleae Logic Pro for the first 6 packets

Best regards,

Ming

Hello Ming,

I verified with an oscilloscope the SPI bus. As you can see in the captures below the first 6 packets are not empty. 

The green signal is the clock and the blue one MOSI. I verified also the CS but I had a problem with the 3rd probe and could not have all three signals together (verified that it works fine).

Does that mean the issue is in the AM273x? Is there maybe something wrong in the AM273x configuration?

Best regards,

Dimitra

Hello again,

I managed to get all SPI bus signals in the oscilloscope. In the pictures below are shown CS(yellow), CLK(green) and MOSI(purple).

The picture below shows one part of the first data that were received in the same run where the oscilloscope pictures have been taken.

The problem insists. Why does that happen?

Best regards,

Dimitra

Hi Ming,

Do you have any news regarding my issue?

Best regards,

Dimitra

Hi Dimitra,

Can you try to change the "Frame Format" (Mode 0/1/2/3 etc.):

Best regards,

Ming