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TDA4AH-Q1: TDA4 MMC VENDOR_REGISTER offset

Dariusz Gasiorowski
Prodigy 150 points

Part Number: TDA4AH-Q1

Hi,

I want to use HS400ES mode for eMMC - TDA4 SoC (j784S4).

In PDK  \src\ti\drv\mmcsd\src\v2\MMCSD_v2.c is 

 if(enhancedStrobe)
 {
           HSMMCSDEnhancedStrobeSet(hwAttrs->baseAddr,MMC_VREG_STROBE_ENABLE);
 }

and in src\ti\csl\src\ip\mmc\V4\priv\mmcsd.c is:

int32_t HSMMCSDEnhancedStrobeSet(uintptr_t baseAddr, uint32_t state)
{
....
 SdhcWriteRegisterFieldValueDWord(baseAddr + MMC_VREG, MMC_VREG_STROBE_SHIFT,
					       MMC_VREG_STROBE_MASK, state);
...
}

My question is related to MMC_VREG osffset. In pdk (also latest) is defined in hw_mcc.h as 0x78 while  I found in dockumentation that is defined as MMCSD0_VENDOR_REGISTER Register (Offset = F8h).

And seems 0xF8 is a proper vendor register. Could you please double check what value is proper in context also rest MMC offsets ?

 When I read

0x04f800f8 I get 0x00004e20 (befeore I set strobe bit 0)

 and for

0x04f80078 I get 0x00000000

 

Regards,

Dariusz Gasiorowski

  • +1
    TI__Mastermind 19080 points

    Hi Dariusz,

    Yes, you are correct.

    In addition to that, I also found out that the register offset for MMC_SHAREDBUSCONTROL macro must be 0x0e6 instead of 0x0e0

    Thank you for pointing out these bugs out, Dariusz.

    Best Regards

    Gokul Praveen

  • 0 in reply to Gokul Praveen
    Prodigy 150 points

    Hi Gokul,

    Thank you for the confirmation.

    Seems is also defined MMC_REV as 0xFC but maybe should be defined as MMCSD0_HOST_CONTROLLER_VER Register (Offset = FEh) ? If yes then this is 16 bit register, not 32bit, so then the mask and shift also should be changed, however  function HSMMCSDHCVersion(uintptr_t baseAddr, stSDMMCHCVersion *verInfo) where this is used is not called currently.

    And below is probably correct:

    The MMC_CMD  0x0c is mapped to MMCSD0_TRANSFER_MODE Register (Offset = Ch) and used also with +2  for access to MMCSD0_COMMAND Register (Offset = Eh).

    Regards,

    Dariusz Gasiorowski

  • 0 in reply to Dariusz Gasiorowski
    TI__Mastermind 19080 points

    Hi Dariusz,

    Dariusz Gasiorowski said:
    Seems is also defined MMC_REV as 0xFC but maybe should be defined as MMCSD0_HOST_CONTROLLER_VER Register (Offset = FEh) ? If yes then this is 16 bit register, not 32bit, so then the mask and shift also should be changed, however  function HSMMCSDHCVersion(uintptr_t baseAddr, stSDMMCHCVersion *verInfo) where this is used is not called currently.

    Actually, this is correct because we are trying to read DWORD(32 bits). Hence, the MMCSD0_HOST_CONTROLLER_VER register would be the MSB 16 bits of the value read into the regValue variable.

    The MMC_REV_SREV_SHIFT(shifts 16 bits to the right) and the MMC_REV_VREV_SHIFT(Shifts 24 bits to the right) would also be correct in this case then as the SPEC_VER_NUM is bit 0-7 and VEN_VER_NUM bits is bit 8-15.

     

    Dariusz Gasiorowski said:

    And below is probably correct:

    The MMC_CMD  0x0c is mapped to MMCSD0_TRANSFER_MODE Register (Offset = Ch) and used also with +2  for access to MMCSD0_COMMAND Register (Offset = Eh).

    Yes, this is correct, Dariusz as +2 is being used to access the MMCSD0_Command registers.

    Best Regards

    Gokul Praveen

  • 0 in reply to Gokul Praveen
    Prodigy 150 points

    Hi Gokul,

    Yes you right, thanks for this point.

    It seems that the remaining registers are used in a similar way. Could you confirm that the rest access is also correct ?

    Regards,

    Dariusz Gasiorowski

  • +1 in reply to Dariusz Gasiorowski
    TI__Mastermind 19080 points

    Hi Dariusz,

    Yes, I believe that the remaining registers are correct.

    Best Regards

    Gokul Praveen