Part Number: DRA821U
Other Parts Discussed in Thread: SYSCONFIG
We are using the DRA821U MCSPI interface to communicate with FPGAs on our board. Each SPI transaction is a 64-cycle frame where chip select is continuously active.
Each transaction is always either a Read or a Write operation.
In the first 32 cycles, we always send the target Address. In the second 32 cycles we either send the data to for Write, or we receive the Read data back.
We are seeing behavior we are not expecting in the transactions:
1) The Chip Select signal is active (low) for roughly 5 times longer than the transaction itself (when the SPI clock is running)
a. Can the inactive period be shortened?
b. What is causing the extended cycle time relative to the actual active bus time?
2) The SPI clock stalls in the middle of the transaction
a. Can the SPI clock be configured to run continuously. If no, is it possible to configure the clock to run continuously while the chip select is active?
Please see the attached images showing both concerns. Both of these issues impact our overall performance on long data transfers.
Please advise if there are controls that can be set to address these concerns.
