Use EMIF16 as interface for FPGA

I had no experience with this chip so far, but don't see, why it might not work. The only consideration is that EMIF16 speed and bitwidth might be too low comparing to processing power of KeyStone device

Greetings,

From EMIF16 DS

EMIF16 is clocked at CPU/6 frequency. So, for a device running at 1GHz, EMIF16 is

clocked at 166.67 MHz. All references to clock/clock cycles are in terms of EMIF16

clock cycles.

Accordingly, your effective speed at best is 1/3 the 166.67 MHz, due to the nature of the interface, and likely a lot slower when routing and interface effects come to play.

From then you will need to ascertain if this is adequate interface for your design between the Keystone and the FPGA.

Good Luck,

Sam

Yes, the EMIF16 is commonly used in Async SRAM mode to work w/ an FPGA in this manner if the performance of the EMIF suits the needs of the application because it doesn't require the high speed IOs that many of the SerDes based interfaces require and thus it can be implemented on less expensive FPGAs. 

As was pointed out the interface speed will be much slower than interfaces such as SRIO, PCIe, etc. 

Please see the data manual for the specific timing information, Here is the calculation on the theoretical read throughput of the EMIF16. 

The minimum time for entire read cycle i.e. setup + strobe + hold is 50ns.

At 1.25GHz, EMIF16 clock = CPU/6 =>  4.8ns.

So r_setup + r_strobe + r_hold = 50/4.8 = 11 rounded up.

So it takes a minimum of 11 complete CPU/6 clock cycles for one read access, so the actual time for the entire read cycle = 4.8 * 11 = 52.8ns.

For 16-bit wide interface, the theoretical max read throughput = 16/52.8 = 303.03 Mbps

At 1GHz, EMIF16 clock period = 6ns.

Using the same calculation as above, we get theoretical max read throughput = 16/54 = 296.29 Mbps

Best Regards,

Chad

Chad,

Hi, I am new to the EMIF16 IF and would like to ask if you could explain how you derived the value of 50ns in your post above? Does that value apply to every DSP with a EMIF16 IF? Can you tell me what page in the EMIF16 manaul gives this timing information?

Thank you very much,

joe

Chad,

HI, things are clearing up a little. I've been looking voer page 201 in the Data sheet for the TMS320C6655/57. This page discusses the EMIF16 Peripheral. I understand that the values of RS, RST and RSH are programmable. For example the equation: tosu (Output setup time from CE low to Oe low in select strobke mode, SS=1 is (RS+1)*E-3 for the minimum. What I'm confused with is the value for E. In your calculation for a read was 50ns, is that also for a write? Last, did you use RS=RST=RSH = 1?

thanks,

joe

Hello Joe,

The 50ns was a ballpark estimate for the typical cycle time for Async memory devices at the time the TI DSP was announced.

In reality, you will need to check the read/write cycle times of the specific memory device/FPGA that you plan to use (usually found in the respective datasheets) and program the EMIF timing parameters accordingly.