TDA2EG-17: TDA2EG-17 Boot Issue With TDA2Ex Build Configuration.

Hello,
Due to a regional holiday, half of our team is currently out of office. Please expect a 2 day delay in responses. Apologies for the delay and we appreciate your patience.

Thanks Christina,

Update related thread,

[Update 1]

I found customer post this issue two month ago.

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1592446/tda2eg-17-require-ti-secure-tool-for-making-the-signed-mlo?tisearch=e2e-sitesearch&keymatch=tda2eG%2525252017%25252520SECURE%25252520BOOT#

I think it is not secure device.

[Update 2]

TDA2EGBHQCBDQ1 belongs SR2.1 (device version), but I found "Errata K version" do not have any update for SR 2.1

What's different between SR2.0 and SR2.1? 

https://www.ti.com/lit/er/sprz397k/sprz397k.pdf?ts=1768543357590&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTDA2EG-17%253FkeyMatch%253Dtda2%2526tisearch%253Duniversal_search%2526usecase%253Dpartmatches

[Update3]

I suspect the version  "PROCESSOR_SDK_VISION_03_08_00_0" do not add SW patch for SR2.1,. it may caused setting voltage railed failed.

May you confirm does it need SR2.1 patch?

Thank You.

Gibbs 

Hello, TI Expert

May I have your suggestion?

Thank You.

Gibbs

Hello Gibbs,

Will take a look at your thread this week.

-Josue

Gibbs,

If I understand correctly from this comment that you are actually booting one of these parts but not the other?

Gibbs Shih said:

here are two different lot code w/ TDA2EGBHQCBDQ1. Customer claimed LOT code 69P16CQ can boot on customerized board, but 26P1N8Q can not boot. Does both of them have the same ROM code version?

 

They are both TDAEGBHQCBDQ1, only difference being the lot number?

Second, could you please check for both parts the DIE_ID, JTAG ID, and AVS EFuse values?

-Josue

Hi, Josue

Thanks your replies.

I also prefer to dump IE_ID, JTAG ID, and AVS EFuse from register reading, but there is still a JTAG connection issue on customerized board. so base on current status, it's only support SD boot w/ SBL , and then use "printf function" (SBLLibPrintf)  in code for debugging.

Here are some debug updates.

(1) Customer's board can boot with "OPP NOM" SBL binary, but we still face some init failed issues. build(boot) binary path as below,

/home/gibbs/work/TDA2EG-17/PROCESSOR_SDK_VISION_03_08_00_00/vision_sdk/binaries/apps/tda2ex_evm_bios_all/sbl/sd/opp_nom/tda2ex-evm/MLO

(2) I think SBL correct recogized device "TDA2EG-17" , because this function return "TRUE" as below.

SBLLIB_SILICON_PACKAGE_TYPE_17X17 == SBLLibGetSiliconPackageType()

(3) Initial failed in this function "SBLUtilsConfigAllVoltageRails(oppId)", and I found boot crash in "ABB LDO FBB setting", code crash location as below.

        /*
         * Set ABB LDO FBB mode.
         */
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] Set ABB LDO FBB mode\n");
        HW_WR_FIELD32(opp->prmABBLDOSetupRegAddr,
                      PRM_ABBLDO_DSPEVE_SETUP_ACTIVE_FBB_SEL,
                      PRM_ABBLDO_DSPEVE_SETUP_ACTIVE_FBB_SEL_FBB);

Few question & support need :

(1) Beside JTAG debugging, do we have another way to dump E_ID, JTAG ID, and AVS EFuse value from register? becase this function "SBLLibPrintf" only support string output W/O additional arguments.

(2) Customer use LP87332 and LP873220 for PMIC power supply, does this design workable for PROCESSOR_SDK_VISION_03_08_00_0 default code setting? Any modification requirment?

(4) I think PMIC I2C communication should be work well, because I found PMIC function regiser is OK, code as below

it return success.

        if(SBLLIB_SILICON_PACKAGE_TYPE_17X17 == SBLLibGetSiliconPackageType())
    {
        /* This is J6Eco 17X17 Evm. PMIC used is LP8733/32.
         * Register the regulator map as connected on J6Eco 17X17 Evm.
         */
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17 \n");
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->pmicOps = PMHALLP8733GetPMICOps()\n"); 
        PMHALLP8733ConfigureRegulatorMap(gJ6Eco17x17LP8733RegulatorTable);
        pmicOps = PMHALLP8733GetPMICOps();

        //Gibbs
        //pmicOps->isPresent();
   
    }
    
    
    retVal = PMHALPmicRegister(pmicOps);
    if(retVal == PM_SUCCESS){
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][sbl_utils_tda2xx.c] PMHALPmicRegister() ok\n");
    }else{
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][sbl_utils_tda2xx.c] PMHALPmicRegister() failed\n");
    }

Thank You.

Gibbs

Gibbs,

Thank you for the updates. 

Gibbs Shih said:

Customer's board can boot with "OPP NOM" SBL binary, but we still face some init failed issues. build(boot) binary path as below,

So both lots are booting now?

Is one getting further than the other?

Gibbs Shih said:

I think SBL correct recogized device "TDA2EG-17" , because this function return "TRUE" as below.

Same question from above.. does this happen for both lots? If it does than there is no issue with the SW 

With regards to your questions:

(1) I will have to look into it and get back to you.

(3 &4) Should be fine.. See the following App note I found: LP8733-Q1 and LP8732-Q1 User’s Guide to Power DRA71x, DRA79x, and TDA2E-17

Gibbs Shih said:

stop in "SBL initial configure failed.", I think this error is expected because of different TDA2 device has different voltage rails setting.

Is this the only prints you get?

Is this a new bring up? Do you have a working set up?

-Josue

HI, Josue

Replies as below.

Q1/A1 : Is one getting further than the other? So both lots are booting now? 

Customer claim they do not do any HW & SW design change on their customerizes board, so the only different is TDA2 "LOT code".

Customer use ROCESSOR_SDK_VISION_03_07_x, it can boot on LOT code "69P16CQ ", but it "can not" boot for LOT code "26P1N8Q"

Because I suspect it may be "SW compatible problem" between TDA2 ROM code and vision SDK, so I try to update to the latest SDK version (ROCESSOR_SDK_VISION_03_08_x) for testing.

I only make a boot testing for ROCESSOR_SDK_VISION_03_08_x and LOT code "26P1N8Q". I try to add some print function in code, and then it boots even boot still crash finally.

I think SBL source code do not have much different between SDK_VISION_03_07_x and SDK_VISION_03_08_x after I try to compare these two different version.

Q2/A2 : Is this the only prints you get?

Share some code that I modificiation before (as attachment) , you can see only add "SBLLibPrintf"

Sorry, because JTAG do not work, so I use print function to diagnostic the issue.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/tda2eg_5F00_test_5F00_code.tgz

Boot log as below, boot crash may be in "PMHALVMInitABB()" function, so far I have no idea.

You can search key word "Gibbs" to trace these log.

program stops (crash) in this string "[Gibbs][pmhal_vm.c] Set ABB LDO FBB mode".

Welcome to minicom 2.7.1

OPTIONS: I18n 
Compiled on Dec 23 2019, 02:06:26.
Port /dev/ttyUSB0, 11:50:44

Press CTRL-A Z for help on special keys

��
[Gibbs][sbl_tda2ex_main.c] TDA2EX UART1_INST INIT

[Gibbs][sbl_tda2ex_main.c] This project is define SOC_TDA2EX

[Gibbs][sbl_tda2ex_main.c] sblBuildMode = SBLLIB_SBL_BUILD_MODE_DEV

[Gibbs][sbl_tda2ex_main.c] ARM_CCNT_Enable, reset PMU CLOCK counter

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId()

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId not define SOC_TDA2XX

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId, oppId = SBLLIB_PRCM_DPLL_OPP_NOM

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] Enter SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex_17x17

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->PMHALI2CCommRegister()

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17 

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->pmicOps = PMHALLP8733GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733ConfigureRegulatorMap()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733IsPresent()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetVendorId()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetProductId()

[Gibbs][sbl_utils_tda2xx.c] PMHALPmicRegister() ok

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRevision()

[Gibbs][pmhal_lp8733.c] PMHALPmicCommConfigure() success

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733ReadPhyAddr() success

[Gibbs][sbl_utils_tda2xx.c] Get the VD rail info based on the current board

[Gibbs][sbl_utils_tda2xx.c] defined SOC_TDA2EX

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17 

[Gibbs][sbl_utils_tda2xx.c] In SBLUtilsConfigAllVoltageRails()->vdInfoObj = &vdInfo_tda2ex_17x17

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[0].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[1].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[2].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[3].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[4].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] ENTER_11

[Gibbs][sbl_utils_tda2xx.c] ENTER_12

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_15

[Gibbs][sbl_utils_tda2xx.c] ENTER_16

[Gibbs][sbl_utils_tda2xx.c] enter SblUtilsConfigGangedVdRails()

[Gibbs][sbl_utils_tda2xx.c] configOpp = PMHAL_VM_OPP_NOM

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][pmhal_vm.c] pmhalVmGetOppVoltage() start

[Gibbs][pmhal_vm.c] PMHALVMGetAVS0EfuseVoltage() ok 

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][pmhal_vm.c] PPMHALVMGetCurrentVoltage() ok 

[Gibbs][pmhal_vm.c] isABBSupported == TRUE 

[Gibbs][pmhal_vm.c] PMHALPmicSetRegulatorVoltage() 

[Gibbs][pmhal_lp8733.c] PMHALLP8733SetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PMHALLP8733EnableRegulator()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VoltageToVselOffset()

[Gibbs][pmhal_lp8733.c] PmhalLP8733WritePhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][sbl_utils_tda2xx.c] PPMHALVMSetOpp() success

[Gibbs][sbl_utils_tda2xx.c]PMHALVMEnableABB() start

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetVoltageDomai() 

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetOppVoltage() 

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PMHALVMInitABB() 

[Gibbs][pmhal_vm.c] Clear retVal of PRCM interrupt for ABB LDO transition completion

[Gibbs][pmhal_vm.c] Set ABB LDO FBB mode

Many Thanks

Gibbs

Hi, Josue

This is an update.

I solve JTAG connection failed problems, it's wiring issues.

I try to dump some register, ref as below.  (ex, Die_ID)

\

SR 2.1 version,

Pls let me know if you need more related register information.

Thank You.

Gibbs

Thanks Gibbs. Will take a look this week.

Thanks Jouse's alignment

debug is ongoing, this is debug status update.

I use CCS for debuging, recording as below.

This video show some clues,

(1) We use JTAG dynamic load/run SBL, it seems SBL boot completely even we still found SBL config  init failed.

(2) SBL boot from SD, SBL crash in set ABB LDO FBB mode  

Gibbs

Gibbs,

From video, on number 8 you can just click on bypass option for all the cores that you don't want to be initialized with the GEL file.

Can you please try this with all cores? and see if that makes a difference? 

So if I understand correctly the part number that boots all the way is the one with Lot code 89P16CQ? (Our team checked internally and the lot code starting with a 6 does not exist).

Also, I believe there is not any difference in ROM code, so this would not be the issue.

Can you share logs of a successful boot of lot code 89P16CQ?

-Josue

Hi, Jouse.

Thanks your replies, update as below.

(1) Your understanding is correct. "89P16CQ" is correct boot LOT code. this is my mistake.

(2) Sorry I don not have device  LOT code "89P16CQ" on my hand, I can only test on LOT code "26P1N8Q"

(3) Base on lot code "26P1N8Q" device, I initialized TDA2EG-17 with CCS by default GEL, and load program for each cores, its seems fine.

May I say there is no issues on SoC which w/ ROM code?  so we need to dedicated debug Board PCBA (schematic) or SBL source code?

CCS Console as below.

Cortex_M4_IPU1_C0: GEL Output: --->>> TDA2Ex Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA2Ex Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> TDA2Ex Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> TDA2Ex Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> TDA2Ex Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> TDA2Ex Cortex M4 Startup Sequence DONE! <<<---
C66xx_DSP1: GEL Output: --->>> TDA2Ex C66x DSP Startup Sequence In Progress... <<<---
C66xx_DSP1: GEL Output: --->>> TDA2Ex C66x DSP Startup Sequence DONE! <<<---
CortexA15_0: GEL Output: --->>> TDA2Ex Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_0: GEL Output: --->>> TDA2Ex Cortex A15 Startup Sequence DONE! <<<---
IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset. 
IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset. 
CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs  <<<---
CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz 
CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----
CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---
CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----
CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do.
CortexA15_0: GEL Output: --->>> TDA2Ex Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL Output: 	--->>> TDA2Ex PG2.1 GP device <<<---
CortexA15_0: GEL Output: 	--->>> The core is in non-SECURE state. <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	Cortex A15 DPLL is already locked, now unlocking...  
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	PER DPLL already locked, now unlocking  
CortexA15_0: GEL Output: 	PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	CORE DPLL OPP  already locked, now unlocking....  
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: 	DDR DPLL clock config for 666MHz is in progress...
CortexA15_0: GEL Output: 	DDR DPLL clock config for 666MHz is in DONE!
CortexA15_0: GEL Output:        Launch full leveling
CortexA15_0: GEL Output:        Updating slave ratios in PHY_STATUSx registers
CortexA15_0: GEL Output:        as per HW leveling output
CortexA15_0: GEL Output:        HW leveling is now disabled. Using slave ratios from 
CortexA15_0: GEL Output:        PHY_STATUSx registers
CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> TDA2Ex Begin All Pad Configuration for Vision Platform <<<---
CortexA15_0: GEL Output: --->>> TDA2Ex Begin All Pad Configuration for RGMII usage on EVM Platform <<<---
CortexA15_0: GEL Output: 	--->>> TDA2Ex Begin GMAC_SW MDIO Pad Configuration <<<---
CortexA15_0: GEL Output: 	--->>> TDA2Ex End GMAC_SW MDIO Pad Configuration <<<---
CortexA15_0: GEL Output: 	--->>> TDA2Ex Begin GMAC_SW RGMII0 Pad Configuration <<<---
CortexA15_0: GEL Output: 	--->>> TDA2Ex End GMAC_SW RGMII0 Pad Configuration <<<---
CortexA15_0: GEL Output: 	--->>> TDA2Ex Begin GMAC_SW RGMII1 Pad Configuration <<<---
CortexA15_0: GEL Output: 	--->>> TDA2Ex End GMAC_SW RGMII1 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> TDA2Ex End All Pad Configuration for RGMII usage on EVM Platform <<<---
CortexA15_0: GEL Output: --->>> TDA2Ex End All Pad Configuration for Vision Platform <<<---
CortexA15_0: GEL Output: --->>> TDA2Ex Target Connect Sequence DONE !!!!!  <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	Cortex A15 DPLL is already locked, now unlocking...  
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	IVA DPLL already locked, now unlocking...
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	PER DPLL already locked, now unlocking  
CortexA15_0: GEL Output: 	PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	CORE DPLL OPP  already locked, now unlocking....  
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	ABE DPLL OPP is already locked, now unlocking....
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GMAC DPLL already locked, now unlocking....
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GPU DPLL already locked, now unlocking...
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	DSP DPLL already locked, now unlocking....
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	PCIE_REF DPLL already locked, now unlocking....
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---
CortexA15_0: GEL Output: MPU Temperature:    55.1039009 degC
CortexA15_0: GEL Output: GPU Temperature:    54.2944984 degC
CortexA15_0: GEL Output: CORE Temperature:   55.5085983 degC
CortexA15_0: GEL Output: DSPEVE Temperature: 54.2944984 degC
CortexA15_0: GEL Output: IVA Temperature:    54.6991997 degC

(4) I try to download (+execute) SBL by JTAG on device LOT code "26P1N8Q", uart log output as below.

Welcome to minicom 2.7.1

OPTIONS: I18n 
Compiled on Dec 23 2019, 02:06:26.
Port /dev/ttyUSB0, 11:18:59

Press CTRL-A Z for help on special keys


[Gibbs][sbl_tda2ex_main.c] TDA2EX UART1_INST INIT

[Gibbs][sbl_tda2ex_main.c] This project is define SOC_TDA2EX

[Gibbs][sbl_tda2ex_main.c] sblBuildMode = SBLLIB_SBL_BUILD_MODE_DEV

[Gibbs][sbl_tda2ex_main.c] ARM_CCNT_Enable, reset PMU CLOCK counter

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId()

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId not define SOC_TDA2XX

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId, oppId = SBLLIB_PRCM_DPLL_OPP_NOM

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] Enter SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex_17x17

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->PMHALI2CCommRegister()

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17 

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->pmicOps = PMHALLP8733GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733ConfigureRegulatorMap()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733IsPresent()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetVendorId()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetProductId()

[Gibbs][sbl_utils_tda2xx.c] PMHALPmicRegister() ok

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRevision()

[Gibbs][pmhal_lp8733.c] PMHALPmicCommConfigure() success

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733ReadPhyAddr() success

[Gibbs][sbl_utils_tda2xx.c] Get the VD rail info based on the current board

[Gibbs][sbl_utils_tda2xx.c] defined SOC_TDA2EX

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17 

[Gibbs][sbl_utils_tda2xx.c] In SBLUtilsConfigAllVoltageRails()->vdInfoObj = &vdInfo_tda2ex_17x17

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[0].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[1].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[2].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[3].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[4].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] ENTER_11

[Gibbs][sbl_utils_tda2xx.c] ENTER_12

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_15

[Gibbs][sbl_utils_tda2xx.c] ENTER_16

[Gibbs][sbl_utils_tda2xx.c] enter SblUtilsConfigGangedVdRails()

[Gibbs][sbl_utils_tda2xx.c] configOpp = PMHAL_VM_OPP_NOM

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][pmhal_vm.c] pmhalVmGetOppVoltage() start

[Gibbs][pmhal_vm.c] PMHALVMGetAVS0EfuseVoltage() ok 

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][sbl_utils_tda2xx.c] PPMHALVMSetOpp() success

[Gibbs][sbl_utils_tda2xx.c]PMHALVMEnableABB() start

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetVoltageDomai() 

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetOppVoltage() 

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PMHALVMInitABB() 

[Gibbs][pmhal_vm.c] Clear retVal of PRCM interrupt for ABB LDO transition completion

[Gibbs][pmhal_vm.c] Set ABB LDO FBB mode

[Gibbs][pmhal_vm.c] Ensure OPP_CHANGE is set to 0U and set OPP_SEL to Fast OPP

[Gibbs][pmhal_vm.c] Read the ABB VSET value from the efuse

[Gibbs][pmhal_vm.c] Clear interrupt retVal

[Gibbs][sbl_utils_tda2xx.c] break

[Gibbs] ENTER_17

[Gibbs][sbl_utils_tda2xx.c] SblUtilsConfigGangedVdRails failed

[Gibbs][sbl_utils_tda2xx.c] In SBLUtilsConfigAllVoltageRails()->SblUtilsMMCSDLdoPowerOn()

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails failed

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigPowerDomains() ok

[Gibbs][sbl_tda2ex_main.c] SSBLLibUnlockControlModuleMMR()

[Gibbs][sbl_tda2ex_main.c] Intc_Init()

[Gibbs][sbl_tda2ex_main.c] Intc_IntEnable()

[Gibbs][sbl_tda2ex_main.c] SBLUtilsWDTimerBegin()

[Gibbs][sbl_tda2ex_main.c] SBLLibGetDpllStructure() ok

[Gibbs][sbl_tda2ex_main.c] PMHALCMMuxParentSelect()

[Gibbs][sbl_tda2ex_main.c] PMHALCMDpllConfigure() ok

[Gibbs][sbl_tda2ex_main.c] PSBLLibGetDpllStructure() ok

[Gibbs][sbl_tda2ex_main.c] PMHALCMDpllConfigure() ok

[Gibbs][sbl_tda2ex_main.c] TDA2Ex SBL Boot 

[Gibbs][sbl_tda2ex_main.c] SBLLibHSOpenL3Firewalls()

 [Gibbs][sbl_tda2ex_main.c] SBL Initial Config Failed 

[Gibbs][sbl_tda2ex_main.c] Configure DPLLS

 DPLL Configuration Completed 

[Gibbs][sbl_tda2ex_main.c] Configure CLOCK DOMAINS

 Clock Domain Configuration Completed 

[Gibbs][sbl_tda2ex_main.c] Configure CLOCK MODULES

 Module Enable Configuration Completed 

[Gibbs][sbl_tda2ex_main.c] Configure SBLConfigTIEVMPad()

 TI EVM PAD Config Completed 

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigStaticDependency() ok

[Gibbs][sbl_tda2ex_main.c] Configure SBLUtilsDDR3Config()

 DDR Config Completed 

[Gibbs][sbl_tda2ex_main.c] Initialize the EDMA

[Gibbs][sbl_tda2ex_main.c] Reset the slave cores 

[Gibbs][sbl_tda2ex_main.c] App Image Download Begins 

 SD Boot - File open fails 

 Valid App Image is not Available 

*****************************************************************

 PMCCNTR counts once every 64 clock cycles, multiple by 64 to get actual CPU cycles 

 SBL Initial Config Cycles - 5809775  (464.78 ms)
 SOC Init Cycles - 491840  (39.34 ms)
 DDR Config Clock Cycles - 114505  (9.16 ms)
 App Image Load Cycles - 487488  (38.99 ms)
 Slave Core Bootup Cycles - 14642  (1.17 ms)
 SBL Boot-up Cycles - 6920787  (553.66 ms)
 Time at which SBL started IPU1_0 - 6359949  (508.79 ms)
*****************************************************************

�Putting MPU in Retention... 
[Gibbs][sbl_tda2ex_main.c] TDA2EX UART1_INST INIT

[Gibbs][sbl_tda2ex_main.c] This project is define SOC_TDA2EX

[Gibbs][sbl_tda2ex_main.c] sblBuildMode = SBLLIB_SBL_BUILD_MODE_DEV

[Gibbs][sbl_tda2ex_main.c] ARM_CCNT_Enable, reset PMU CLOCK counter

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId()

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId not define SOC_TDA2XX

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId, oppId = SBLLIB_PRCM_DPLL_OPP_NOM

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] Enter SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex_17x17

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->PMHALI2CCommRegister()

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17 

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->pmicOps = PMHALLP8733GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733ConfigureRegulatorMap()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733IsPresent()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetVendorId()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetProductId()

[Gibbs][sbl_utils_tda2xx.c] PMHALPmicRegister() ok

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRevision()

[Gibbs][pmhal_lp8733.c] PMHALPmicCommConfigure() success

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733ReadPhyAddr() success

[Gibbs][sbl_utils_tda2xx.c] Get the VD rail info based on the current board

[Gibbs][sbl_utils_tda2xx.c] defined SOC_TDA2EX

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17 

[Gibbs][sbl_utils_tda2xx.c] In SBLUtilsConfigAllVoltageRails()->vdInfoObj = &vdInfo_tda2ex_17x17

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[0].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[1].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[2].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[3].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[4].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] ENTER_11

[Gibbs][sbl_utils_tda2xx.c] ENTER_12

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_15

[Gibbs][sbl_utils_tda2xx.c] ENTER_16

[Gibbs][sbl_utils_tda2xx.c] enter SblUtilsConfigGangedVdRails()

[Gibbs][sbl_utils_tda2xx.c] configOpp = PMHAL_VM_OPP_NOM

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][pmhal_vm.c] pmhalVmGetOppVoltage() start

[Gibbs][pmhal_vm.c] PMHALVMGetAVS0EfuseVoltage() ok 

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][sbl_utils_tda2xx.c] PPMHALVMSetOpp() success

[Gibbs][sbl_utils_tda2xx.c]PMHALVMEnableABB() start

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetVoltageDomai() 

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetOppVoltage() 

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PMHALVMInitABB() 

[Gibbs][pmhal_vm.c] Clear retVal of PRCM interrupt for ABB LDO transition completion

[Gibbs][pmhal_vm.c] Set ABB LDO FBB mode

[Gibbs][pmhal_vm.c] Ensure OPP_CHANGE is set to 0U and set OPP_SEL to Fast OPP

[Gibbs][pmhal_vm.c] Read the ABB VSET value from the efuse

[Gibbs][pmhal_vm.c] Clear interrupt retVal

[Gibbs][sbl_utils_tda2xx.c] break

[Gibbs] ENTER_17

[Gibbs][sbl_utils_tda2xx.c] SblUtilsConfigGangedVdRails failed

[Gibbs][sbl_utils_tda2xx.c] In SBLUtilsConfigAllVoltageRails()->SblUtilsMMCSDLdoPowerOn()

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails failed

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigPowerDomains() ok

[Gibbs][sbl_tda2ex_main.c] SSBLLibUnlockControlModuleMMR()

[Gibbs][sbl_tda2ex_main.c] Intc_Init()

[Gibbs][sbl_tda2ex_main.c] Intc_IntEnable()

[Gibbs][sbl_tda2ex_main.c] SBLUtilsWDTimerBegin()

[Gibbs][sbl_tda2ex_main.c] SBLLibGetDpllStructure() ok

[Gibbs][sbl_tda2ex_main.c] PMHALCMMuxParentSelect()

[Gibbs][sbl_tda2ex_main.c] PMHALCMDpllConfigure() ok

[Gibbs][sbl_tda2ex_main.c] PSBLLibGetDpllStructure() ok

[Gibbs][sbl_tda2ex_main.c] PMHALCMDpllConfigure() ok

[Gibbs][sbl_tda2ex_main.c] TDA2Ex SBL Boot 

[Gibbs][sbl_tda2ex_main.c] SBLLibHSOpenL3Firewalls()

 [Gibbs][sbl_tda2ex_main.c] SBL Initial Config Failed 

[Gibbs][sbl_tda2ex_main.c] Configure DPLLS

 DPLL Configuration Completed 

[Gibbs][sbl_tda2ex_main.c] Configure CLOCK DOMAINS

 Clock Domain Configuration Completed 

[Gibbs][sbl_tda2ex_main.c] Configure CLOCK MODULES

 Module Enable Configuration Completed 

[Gibbs][sbl_tda2ex_main.c] Configure SBLConfigTIEVMPad()

 TI EVM PAD Config Completed 

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigStaticDependency() ok

[Gibbs][sbl_tda2ex_main.c] Configure SBLUtilsDDR3Config()

 DDR Config Completed 

[Gibbs][sbl_tda2ex_main.c] Initialize the EDMA

[Gibbs][sbl_tda2ex_main.c] Reset the slave cores 

[Gibbs][sbl_tda2ex_main.c] App Image Download Begins 

 SD Boot - File open fails 

 Valid App Image is not Available 

*****************************************************************

 PMCCNTR counts once every 64 clock cycles, multiple by 64 to get actual CPU cycles 

 SBL Initial Config Cycles - 5809209  (464.73 ms)
 SOC Init Cycles - 491749  (39.33 ms)
 DDR Config Clock Cycles - 114539  (9.16 ms)
 App Image Load Cycles - 264742  (21.17 ms)
 Slave Core Bootup Cycles - 14776  (1.18 ms)
 SBL Boot-up Cycles - 6697553  (535.80 ms)
 Time at which SBL started IPU1_0 - 6380014  (510.40 ms)
*****************************************************************

 Putting MPU in Retention... 

I think SBL should be boot complete, but we still watch two failed,

(1) --> [Gibbs][sbl_utils_tda2xx.c] SblUtilsConfigGangedVdRails failed

            retVal = SblUtilsConfigGangedVdRails(&gangedVdRails[0],
                                                  numGangedRails,
                                                  oppId);

            SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs] ENTER_17\n");

            if(retVal == PM_SUCCESS){
                SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][sbl_utils_tda2xx.c] SblUtilsConfigGangedVdRails success\n");
            }
            else{
                SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][sbl_utils_tda2xx.c] SblUtilsConfigGangedVdRails failed\n");
            }

(2) --> [Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails failed

    retVal = SBLUtilsConfigAllVoltageRails(oppId);

    if (PM_SUCCESS != retVal)
    {
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails failed\n");
        gSetVoltRailsStatus = STW_EFAIL;
    }

I am not sure we should deep dive these two failed (SblUtilsConfigGangedVdRails / SBLUtilsConfigAllVoltageRails  failed), becuase it only happens when SBL loads by JTAG.

Thanks

Gibbs

Hi, Jouse.

Thanks your replies, update as below.

(1) Your understanding is correct. "89P16CQ" is correct boot LOT code. this is my mistake.

(2) Sorry I don not have device  LOT code "89P16CQ" on my hand, I can only test on LOT code "26P1N8Q"

(3) Base on lot code "26P1N8Q" device, I initialized TDA2EG-17 with CCS by default GEL, and load program for each cores, its seems fine.

May I say there is no issues on SoC which w/ ROM code?  so we need to dedicated debug Board PCBA (schematic) or SBL source code?

CCS Console as below.

Cortex_M4_IPU1_C0: GEL Output: --->>> TDA2Ex Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA2Ex Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> TDA2Ex Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> TDA2Ex Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> TDA2Ex Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> TDA2Ex Cortex M4 Startup Sequence DONE! <<<---
C66xx_DSP1: GEL Output: --->>> TDA2Ex C66x DSP Startup Sequence In Progress... <<<---
C66xx_DSP1: GEL Output: --->>> TDA2Ex C66x DSP Startup Sequence DONE! <<<---
CortexA15_0: GEL Output: --->>> TDA2Ex Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_0: GEL Output: --->>> TDA2Ex Cortex A15 Startup Sequence DONE! <<<---
IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset. 
IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset. 
CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs  <<<---
CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz 
CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----
CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---
CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----
CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do.
CortexA15_0: GEL Output: --->>> TDA2Ex Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL Output: 	--->>> TDA2Ex PG2.1 GP device <<<---
CortexA15_0: GEL Output: 	--->>> The core is in non-SECURE state. <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	Cortex A15 DPLL is already locked, now unlocking...  
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	PER DPLL already locked, now unlocking  
CortexA15_0: GEL Output: 	PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	CORE DPLL OPP  already locked, now unlocking....  
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: 	DDR DPLL clock config for 666MHz is in progress...
CortexA15_0: GEL Output: 	DDR DPLL clock config for 666MHz is in DONE!
CortexA15_0: GEL Output:        Launch full leveling
CortexA15_0: GEL Output:        Updating slave ratios in PHY_STATUSx registers
CortexA15_0: GEL Output:        as per HW leveling output
CortexA15_0: GEL Output:        HW leveling is now disabled. Using slave ratios from 
CortexA15_0: GEL Output:        PHY_STATUSx registers
CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> TDA2Ex Begin All Pad Configuration for Vision Platform <<<---
CortexA15_0: GEL Output: --->>> TDA2Ex Begin All Pad Configuration for RGMII usage on EVM Platform <<<---
CortexA15_0: GEL Output: 	--->>> TDA2Ex Begin GMAC_SW MDIO Pad Configuration <<<---
CortexA15_0: GEL Output: 	--->>> TDA2Ex End GMAC_SW MDIO Pad Configuration <<<---
CortexA15_0: GEL Output: 	--->>> TDA2Ex Begin GMAC_SW RGMII0 Pad Configuration <<<---
CortexA15_0: GEL Output: 	--->>> TDA2Ex End GMAC_SW RGMII0 Pad Configuration <<<---
CortexA15_0: GEL Output: 	--->>> TDA2Ex Begin GMAC_SW RGMII1 Pad Configuration <<<---
CortexA15_0: GEL Output: 	--->>> TDA2Ex End GMAC_SW RGMII1 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> TDA2Ex End All Pad Configuration for RGMII usage on EVM Platform <<<---
CortexA15_0: GEL Output: --->>> TDA2Ex End All Pad Configuration for Vision Platform <<<---
CortexA15_0: GEL Output: --->>> TDA2Ex Target Connect Sequence DONE !!!!!  <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	Cortex A15 DPLL is already locked, now unlocking...  
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	IVA DPLL already locked, now unlocking...
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	PER DPLL already locked, now unlocking  
CortexA15_0: GEL Output: 	PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	CORE DPLL OPP  already locked, now unlocking....  
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	ABE DPLL OPP is already locked, now unlocking....
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GMAC DPLL already locked, now unlocking....
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GPU DPLL already locked, now unlocking...
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	DSP DPLL already locked, now unlocking....
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	PCIE_REF DPLL already locked, now unlocking....
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---
CortexA15_0: GEL Output: MPU Temperature:    55.1039009 degC
CortexA15_0: GEL Output: GPU Temperature:    54.2944984 degC
CortexA15_0: GEL Output: CORE Temperature:   55.5085983 degC
CortexA15_0: GEL Output: DSPEVE Temperature: 54.2944984 degC
CortexA15_0: GEL Output: IVA Temperature:    54.6991997 degC

(4) I try to download (+execute) SBL by JTAG on device LOT code "26P1N8Q", uart log output as below.

Welcome to minicom 2.7.1

OPTIONS: I18n 
Compiled on Dec 23 2019, 02:06:26.
Port /dev/ttyUSB0, 11:18:59

Press CTRL-A Z for help on special keys


[Gibbs][sbl_tda2ex_main.c] TDA2EX UART1_INST INIT

[Gibbs][sbl_tda2ex_main.c] This project is define SOC_TDA2EX

[Gibbs][sbl_tda2ex_main.c] sblBuildMode = SBLLIB_SBL_BUILD_MODE_DEV

[Gibbs][sbl_tda2ex_main.c] ARM_CCNT_Enable, reset PMU CLOCK counter

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId()

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId not define SOC_TDA2XX

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId, oppId = SBLLIB_PRCM_DPLL_OPP_NOM

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] Enter SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex_17x17

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->PMHALI2CCommRegister()

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17 

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->pmicOps = PMHALLP8733GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733ConfigureRegulatorMap()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733IsPresent()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetVendorId()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetProductId()

[Gibbs][sbl_utils_tda2xx.c] PMHALPmicRegister() ok

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRevision()

[Gibbs][pmhal_lp8733.c] PMHALPmicCommConfigure() success

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733ReadPhyAddr() success

[Gibbs][sbl_utils_tda2xx.c] Get the VD rail info based on the current board

[Gibbs][sbl_utils_tda2xx.c] defined SOC_TDA2EX

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17 

[Gibbs][sbl_utils_tda2xx.c] In SBLUtilsConfigAllVoltageRails()->vdInfoObj = &vdInfo_tda2ex_17x17

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[0].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[1].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[2].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[3].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[4].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] ENTER_11

[Gibbs][sbl_utils_tda2xx.c] ENTER_12

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_15

[Gibbs][sbl_utils_tda2xx.c] ENTER_16

[Gibbs][sbl_utils_tda2xx.c] enter SblUtilsConfigGangedVdRails()

[Gibbs][sbl_utils_tda2xx.c] configOpp = PMHAL_VM_OPP_NOM

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][pmhal_vm.c] pmhalVmGetOppVoltage() start

[Gibbs][pmhal_vm.c] PMHALVMGetAVS0EfuseVoltage() ok 

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][sbl_utils_tda2xx.c] PPMHALVMSetOpp() success

[Gibbs][sbl_utils_tda2xx.c]PMHALVMEnableABB() start

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetVoltageDomai() 

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetOppVoltage() 

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PMHALVMInitABB() 

[Gibbs][pmhal_vm.c] Clear retVal of PRCM interrupt for ABB LDO transition completion

[Gibbs][pmhal_vm.c] Set ABB LDO FBB mode

[Gibbs][pmhal_vm.c] Ensure OPP_CHANGE is set to 0U and set OPP_SEL to Fast OPP

[Gibbs][pmhal_vm.c] Read the ABB VSET value from the efuse

[Gibbs][pmhal_vm.c] Clear interrupt retVal

[Gibbs][sbl_utils_tda2xx.c] break

[Gibbs] ENTER_17

[Gibbs][sbl_utils_tda2xx.c] SblUtilsConfigGangedVdRails failed

[Gibbs][sbl_utils_tda2xx.c] In SBLUtilsConfigAllVoltageRails()->SblUtilsMMCSDLdoPowerOn()

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails failed

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigPowerDomains() ok

[Gibbs][sbl_tda2ex_main.c] SSBLLibUnlockControlModuleMMR()

[Gibbs][sbl_tda2ex_main.c] Intc_Init()

[Gibbs][sbl_tda2ex_main.c] Intc_IntEnable()

[Gibbs][sbl_tda2ex_main.c] SBLUtilsWDTimerBegin()

[Gibbs][sbl_tda2ex_main.c] SBLLibGetDpllStructure() ok

[Gibbs][sbl_tda2ex_main.c] PMHALCMMuxParentSelect()

[Gibbs][sbl_tda2ex_main.c] PMHALCMDpllConfigure() ok

[Gibbs][sbl_tda2ex_main.c] PSBLLibGetDpllStructure() ok

[Gibbs][sbl_tda2ex_main.c] PMHALCMDpllConfigure() ok

[Gibbs][sbl_tda2ex_main.c] TDA2Ex SBL Boot 

[Gibbs][sbl_tda2ex_main.c] SBLLibHSOpenL3Firewalls()

 [Gibbs][sbl_tda2ex_main.c] SBL Initial Config Failed 

[Gibbs][sbl_tda2ex_main.c] Configure DPLLS

 DPLL Configuration Completed 

[Gibbs][sbl_tda2ex_main.c] Configure CLOCK DOMAINS

 Clock Domain Configuration Completed 

[Gibbs][sbl_tda2ex_main.c] Configure CLOCK MODULES

 Module Enable Configuration Completed 

[Gibbs][sbl_tda2ex_main.c] Configure SBLConfigTIEVMPad()

 TI EVM PAD Config Completed 

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigStaticDependency() ok

[Gibbs][sbl_tda2ex_main.c] Configure SBLUtilsDDR3Config()

 DDR Config Completed 

[Gibbs][sbl_tda2ex_main.c] Initialize the EDMA

[Gibbs][sbl_tda2ex_main.c] Reset the slave cores 

[Gibbs][sbl_tda2ex_main.c] App Image Download Begins 

 SD Boot - File open fails 

 Valid App Image is not Available 

*****************************************************************

 PMCCNTR counts once every 64 clock cycles, multiple by 64 to get actual CPU cycles 

 SBL Initial Config Cycles - 5809775  (464.78 ms)
 SOC Init Cycles - 491840  (39.34 ms)
 DDR Config Clock Cycles - 114505  (9.16 ms)
 App Image Load Cycles - 487488  (38.99 ms)
 Slave Core Bootup Cycles - 14642  (1.17 ms)
 SBL Boot-up Cycles - 6920787  (553.66 ms)
 Time at which SBL started IPU1_0 - 6359949  (508.79 ms)
*****************************************************************

�Putting MPU in Retention... 
[Gibbs][sbl_tda2ex_main.c] TDA2EX UART1_INST INIT

[Gibbs][sbl_tda2ex_main.c] This project is define SOC_TDA2EX

[Gibbs][sbl_tda2ex_main.c] sblBuildMode = SBLLIB_SBL_BUILD_MODE_DEV

[Gibbs][sbl_tda2ex_main.c] ARM_CCNT_Enable, reset PMU CLOCK counter

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId()

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId not define SOC_TDA2XX

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId, oppId = SBLLIB_PRCM_DPLL_OPP_NOM

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] Enter SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex_17x17

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->PMHALI2CCommRegister()

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17 

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->pmicOps = PMHALLP8733GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733ConfigureRegulatorMap()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733IsPresent()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetVendorId()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetProductId()

[Gibbs][sbl_utils_tda2xx.c] PMHALPmicRegister() ok

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRevision()

[Gibbs][pmhal_lp8733.c] PMHALPmicCommConfigure() success

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733ReadPhyAddr() success

[Gibbs][sbl_utils_tda2xx.c] Get the VD rail info based on the current board

[Gibbs][sbl_utils_tda2xx.c] defined SOC_TDA2EX

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17 

[Gibbs][sbl_utils_tda2xx.c] In SBLUtilsConfigAllVoltageRails()->vdInfoObj = &vdInfo_tda2ex_17x17

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[0].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[1].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[2].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[3].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[4].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] ENTER_11

[Gibbs][sbl_utils_tda2xx.c] ENTER_12

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_15

[Gibbs][sbl_utils_tda2xx.c] ENTER_16

[Gibbs][sbl_utils_tda2xx.c] enter SblUtilsConfigGangedVdRails()

[Gibbs][sbl_utils_tda2xx.c] configOpp = PMHAL_VM_OPP_NOM

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][pmhal_vm.c] pmhalVmGetOppVoltage() start

[Gibbs][pmhal_vm.c] PMHALVMGetAVS0EfuseVoltage() ok 

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][sbl_utils_tda2xx.c] PPMHALVMSetOpp() success

[Gibbs][sbl_utils_tda2xx.c]PMHALVMEnableABB() start

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetVoltageDomai() 

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetOppVoltage() 

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PMHALVMInitABB() 

[Gibbs][pmhal_vm.c] Clear retVal of PRCM interrupt for ABB LDO transition completion

[Gibbs][pmhal_vm.c] Set ABB LDO FBB mode

[Gibbs][pmhal_vm.c] Ensure OPP_CHANGE is set to 0U and set OPP_SEL to Fast OPP

[Gibbs][pmhal_vm.c] Read the ABB VSET value from the efuse

[Gibbs][pmhal_vm.c] Clear interrupt retVal

[Gibbs][sbl_utils_tda2xx.c] break

[Gibbs] ENTER_17

[Gibbs][sbl_utils_tda2xx.c] SblUtilsConfigGangedVdRails failed

[Gibbs][sbl_utils_tda2xx.c] In SBLUtilsConfigAllVoltageRails()->SblUtilsMMCSDLdoPowerOn()

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails failed

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigPowerDomains() ok

[Gibbs][sbl_tda2ex_main.c] SSBLLibUnlockControlModuleMMR()

[Gibbs][sbl_tda2ex_main.c] Intc_Init()

[Gibbs][sbl_tda2ex_main.c] Intc_IntEnable()

[Gibbs][sbl_tda2ex_main.c] SBLUtilsWDTimerBegin()

[Gibbs][sbl_tda2ex_main.c] SBLLibGetDpllStructure() ok

[Gibbs][sbl_tda2ex_main.c] PMHALCMMuxParentSelect()

[Gibbs][sbl_tda2ex_main.c] PMHALCMDpllConfigure() ok

[Gibbs][sbl_tda2ex_main.c] PSBLLibGetDpllStructure() ok

[Gibbs][sbl_tda2ex_main.c] PMHALCMDpllConfigure() ok

[Gibbs][sbl_tda2ex_main.c] TDA2Ex SBL Boot 

[Gibbs][sbl_tda2ex_main.c] SBLLibHSOpenL3Firewalls()

 [Gibbs][sbl_tda2ex_main.c] SBL Initial Config Failed 

[Gibbs][sbl_tda2ex_main.c] Configure DPLLS

 DPLL Configuration Completed 

[Gibbs][sbl_tda2ex_main.c] Configure CLOCK DOMAINS

 Clock Domain Configuration Completed 

[Gibbs][sbl_tda2ex_main.c] Configure CLOCK MODULES

 Module Enable Configuration Completed 

[Gibbs][sbl_tda2ex_main.c] Configure SBLConfigTIEVMPad()

 TI EVM PAD Config Completed 

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigStaticDependency() ok

[Gibbs][sbl_tda2ex_main.c] Configure SBLUtilsDDR3Config()

 DDR Config Completed 

[Gibbs][sbl_tda2ex_main.c] Initialize the EDMA

[Gibbs][sbl_tda2ex_main.c] Reset the slave cores 

[Gibbs][sbl_tda2ex_main.c] App Image Download Begins 

 SD Boot - File open fails 

 Valid App Image is not Available 

*****************************************************************

 PMCCNTR counts once every 64 clock cycles, multiple by 64 to get actual CPU cycles 

 SBL Initial Config Cycles - 5809209  (464.73 ms)
 SOC Init Cycles - 491749  (39.33 ms)
 DDR Config Clock Cycles - 114539  (9.16 ms)
 App Image Load Cycles - 264742  (21.17 ms)
 Slave Core Bootup Cycles - 14776  (1.18 ms)
 SBL Boot-up Cycles - 6697553  (535.80 ms)
 Time at which SBL started IPU1_0 - 6380014  (510.40 ms)
*****************************************************************

 Putting MPU in Retention... 

I think SBL should be boot complete, but we still watch two failed,

(1) --> [Gibbs][sbl_utils_tda2xx.c] SblUtilsConfigGangedVdRails failed

            retVal = SblUtilsConfigGangedVdRails(&gangedVdRails[0],
                                                  numGangedRails,
                                                  oppId);

            SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs] ENTER_17\n");

            if(retVal == PM_SUCCESS){
                SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][sbl_utils_tda2xx.c] SblUtilsConfigGangedVdRails success\n");
            }
            else{
                SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][sbl_utils_tda2xx.c] SblUtilsConfigGangedVdRails failed\n");
            }

(2) --> [Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails failed

    retVal = SBLUtilsConfigAllVoltageRails(oppId);

    if (PM_SUCCESS != retVal)
    {
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails failed\n");
        gSetVoltRailsStatus = STW_EFAIL;
    }

I am not sure we should deep dive these two failed (SblUtilsConfigGangedVdRails / SBLUtilsConfigAllVoltageRails  failed), becuase it only happens when SBL loads by JTAG. But even SBL boot w/ SD or Load by JTAG, both of them is seems have some error for "ABB LDO" votage setting, code definition as below.

pmErrCode_t PMHALVMEnableABB(pmhalPrcmVdId_t voltDomId, pmhalVmOppId_t oppId)

Thanks

Gibbs

Gibbs,

So you only have two devices failing out of how many? whats your failure rate?

Also, could you explain what you mean here? 

Gibbs Shih said:

May I say there is no issues on SoC which w/ ROM code?  so we need to dedicated debug Board PCBA (schematic) or SBL source code?

I don't follow the logic in questions here.

Also, did you assert that these failures only happen during JTAG load, not during SD boot?

-Josue

Hi, Josue

Sorry confuse you.

Let me summarize the Q/A of this thread,

Background Story : 

(1) Customer has two different kinds of lot code device, Both of them are TDA2EG-17. One is 69P16CQ , and the other is 26P1N8Q. 69P16CQ w/SD SBL boots well, but 26P1N8Q is not. Both of two lot code test on "same design" PCBA and SBL binary.

(2) 69P16CQ device is on customer side, I do not bring it back to TI office for testing, but 26P1N8Q does. So all of test and discussion in under 26P1N8Q in TI office.

(3) Customer have second DVT build for 26P1N8Q, total 10 pcs with failed rate 100%, each board boot failed.

(5) The definition of boot failed which mean NO uart console output.

What're customer (or me) thinking?

(6) Is it chip issue? Should we start FA analysis? 

(7) Is it software compatible issues between vision SDK and ROM code?

What's Debug Status : (All of testing are under 26P1N8Q w/ customer board)

(8) Customer have this issues on vision SDK (PROCERSSOR_SDK_VISION_03_07_00), but I try to I download final vision SDK (PROCERSSOR_SDK_VISION_03_08_00), and use this version to build SBL. It already have some uart console output even boot still have issues. I assume final SDK (03_08_00) already have the latest patch update. 

https://www.ti.com/tool/download/PROCESSOR-SDK-VISION

(9) Base on SDK (03_08_00), SBL "SD boot with MLO" on customized board. The uart log as below.

[Gibbs][sbl_tda2ex_main.c] TDA2EX UART1_INST INIT

[Gibbs][sbl_tda2ex_main.c] This project is define SOC_TDA2EX

[Gibbs][sbl_tda2ex_main.c] sblBuildMode = SBLLIB_SBL_BUILD_MODE_DEV

[Gibbs][sbl_tda2ex_main.c] ARM_CCNT_Enable, reset PMU CLOCK counter

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId()

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId not define SOC_TDA2XX

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId, oppId = SBLLIB_PRCM_DPLL_OPP_NOM

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] Enter SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex_17x17

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->PMHALI2CCommRegister()

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17 

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->pmicOps = PMHALLP8733GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733ConfigureRegulatorMap()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733IsPresent()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetVendorId()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetProductId()

[Gibbs][sbl_utils_tda2xx.c] PMHALPmicRegister() ok

[Gibbs][sbl_utils_tda2xx.c] Get the VD rail info based on the current board

[Gibbs][sbl_utils_tda2xx.c] defined SOC_TDA2EX

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17 

[Gibbs][sbl_utils_tda2xx.c] In SBLUtilsConfigAllVoltageRails()->vdInfoObj = &vdInfo_tda2ex_17x17

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[0].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[1].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[2].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[3].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[4].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] ENTER_11

[Gibbs][sbl_utils_tda2xx.c] ENTER_12

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_15

[Gibbs][sbl_utils_tda2xx.c] ENTER_16

[Gibbs][sbl_utils_tda2xx.c] enter SblUtilsConfigGangedVdRails()

[Gibbs][sbl_utils_tda2xx.c] configOpp = PMHAL_VM_OPP_NOM

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][pmhal_vm.c] pmhalVmGetOppVoltage() start

[Gibbs][pmhal_vm.c] PMHALVMGetAVS0EfuseVoltage() ok 

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][pmhal_vm.c] PPMHALVMGetCurrentVoltage() ok 

[Gibbs][pmhal_vm.c] isABBSupported == TRUE 

[Gibbs][pmhal_vm.c] PMHALPmicSetRegulatorVoltage() 

[Gibbs][pmhal_lp8733.c] PMHALLP8733SetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PMHALLP8733EnableRegulator()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VoltageToVselOffset()

[Gibbs][pmhal_lp8733.c] PmhalLP8733WritePhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][sbl_utils_tda2xx.c] PPMHALVMSetOpp() success

[Gibbs][sbl_utils_tda2xx.c]PMHALVMEnableABB() start

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetVoltageDomai() 

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetOppVoltage() 

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PMHALVMInitABB() 

[Gibbs][pmhal_vm.c] Clear retVal of PRCM interrupt for ABB LDO transition completion

[Gibbs][pmhal_vm.c] Set ABB LDO FBB mode

So I try to use JTAG to "load symbols" in CCS, and find crash happen in this code.  

        HW_WR_FIELD32(opp->prmABBLDOSetupRegAddr,
                      PRM_ABBLDO_DSPEVE_SETUP_ACTIVE_FBB_SEL,
                      PRM_ABBLDO_DSPEVE_SETUP_ACTIVE_FBB_SEL_FBB);

(10) Base on SDK (03_08_00), I use JTAG to download SBL to customized board and run it.  (CCS Load program & runs--> sbl_sd_opp_nom_a15_0_release.xa15fg)

The uart log as below.

Welcome to minicom 2.7.1

OPTIONS: I18n 
Compiled on Dec 23 2019, 02:06:26.
Port /dev/ttyUSB0, 17:41:44

Press CTRL-A Z for help on special keys


[Gibbs][sbl_tda2ex_main.c] TDA2EX UART1_INST INIT

[Gibbs][sbl_tda2ex_main.c] This project is define SOC_TDA2EX

[Gibbs][sbl_tda2ex_main.c] sblBuildMode = SBLLIB_SBL_BUILD_MODE_DEV

[Gibbs][sbl_tda2ex_main.c] ARM_CCNT_Enable, reset PMU CLOCK counter

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId()

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId not define SOC_TDA2XX

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId, oppId = SBLLIB_PRCM_DPLL_OPP_NOM

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] Enter SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex_17x17

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->PMHALI2CCommRegister()

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17 

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->pmicOps = PMHALLP8733GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733ConfigureRegulatorMap()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733IsPresent()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetVendorId()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetProductId()

[Gibbs][sbl_utils_tda2xx.c] PMHALPmicRegister() ok

[Gibbs][sbl_utils_tda2xx.c] Get the VD rail info based on the current board

[Gibbs][sbl_utils_tda2xx.c] defined SOC_TDA2EX

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17 

[Gibbs][sbl_utils_tda2xx.c] In SBLUtilsConfigAllVoltageRails()->vdInfoObj = &vdInfo_tda2ex_17x17

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[0].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[1].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[2].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[3].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[4].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] ENTER_11

[Gibbs][sbl_utils_tda2xx.c] ENTER_12

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_15

[Gibbs][sbl_utils_tda2xx.c] ENTER_16

[Gibbs][sbl_utils_tda2xx.c] enter SblUtilsConfigGangedVdRails()

[Gibbs][sbl_utils_tda2xx.c] configOpp = PMHAL_VM_OPP_NOM

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][pmhal_vm.c] pmhalVmGetOppVoltage() start

[Gibbs][pmhal_vm.c] PMHALVMGetAVS0EfuseVoltage() ok 

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][pmhal_vm.c] PPMHALVMGetCurrentVoltage() ok 

[Gibbs][pmhal_vm.c] isABBSupported == TRUE 

[Gibbs][pmhal_vm.c] PMHALPmicSetRegulatorVoltage() 

[Gibbs][pmhal_lp8733.c] PMHALLP8733SetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PMHALLP8733EnableRegulator()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VoltageToVselOffset()

[Gibbs][pmhal_lp8733.c] PmhalLP8733WritePhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][sbl_utils_tda2xx.c] PPMHALVMSetOpp() success

[Gibbs][sbl_utils_tda2xx.c]PMHALVMEnableABB() start

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetVoltageDomai() 

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetOppVoltage() 

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PMHALVMInitABB() 

[Gibbs][pmhal_vm.c] Clear retVal of PRCM interrupt for ABB LDO transition completion

[Gibbs][pmhal_vm.c] Set ABB LDO FBB mode

[Gibbs][pmhal_vm.c] Ensure OPP_CHANGE is set to 0U and set OPP_SEL to Fast OPP

[Gibbs][pmhal_vm.c] Read the ABB VSET value from the efuse

[Gibbs][pmhal_vm.c] PM_TIMEOUT

[Gibbs][pmhal_vm.c] Clear interrupt retVal

[Gibbs][sbl_utils_tda2xx.c] PMHALVMEnableABB failed, break

[Gibbs] ENTER_17

[Gibbs][sbl_utils_tda2xx.c] SblUtilsConfigGangedVdRails failed

[Gibbs][sbl_utils_tda2xx.c] In SBLUtilsConfigAllVoltageRails()->SblUtilsMMCSDLdoPowerOn()

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails failed

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigPowerDomains() ok

[Gibbs][sbl_tda2ex_main.c] SSBLLibUnlockControlModuleMMR()

[Gibbs][sbl_tda2ex_main.c] Intc_Init()

[Gibbs][sbl_tda2ex_main.c] Intc_IntEnable()

[Gibbs][sbl_tda2ex_main.c] SBLUtilsWDTimerBegin()

[Gibbs][sbl_tda2ex_main.c] SBLLibGetDpllStructure() ok

[Gibbs][sbl_tda2ex_main.c] PMHALCMMuxParentSelect()

[Gibbs][sbl_tda2ex_main.c] PMHALCMDpllConfigure() ok

�C�[Gibbs][sbl_tda2ex_main.c] PMHALCMDpllConfigure() ok

[Gibbs][sbl_tda2ex_main.c] TDA2Ex SBL Boot 

[Gibbs][sbl_tda2ex_main.c] SBLLibHSOpenL3Firewalls()

 [Gibbs][sbl_tda2ex_main.c] SBL Initial Config Failed 

[Gibbs][sbl_tda2ex_main.c] Configure DPLLS

 DPLL Configuration Completed 

[Gibbs][sbl_tda2ex_main.c] Configure CLOCK DOMAINS

 Clock Domain Configuration Completed 

[Gibbs][sbl_tda2ex_main.c] Configure CLOCK MODULES

 Module Enable Configuration Completed 

[Gibbs][sbl_tda2ex_main.c] Configure SBLConfigTIEVMPad()

 TI EVM PAD Config Completed 

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigStaticDependency() ok

[Gibbs][sbl_tda2ex_main.c] Configure SBLUtilsDDR3Config()

 DDR Config Completed 

[Gibbs][sbl_tda2ex_main.c] Initialize the EDMA

[Gibbs][sbl_tda2ex_main.c] Reset the slave cores 

[Gibbs][sbl_tda2ex_main.c] App Image Download Begins 

 SD Boot - file open completed successfully 

 MPU CPU0 Image Load Completed 

 IPU1 CPU0 Image Load Completed 

 IPU1 CPU1 Image Load Completed 

 IPU2 CPU0 and CPU1 Image Load Completed 

 DSP1 Image Load Completed 

 App Image Download Completed 

*****************************************************************

 PMCCNTR counts once every 64 clock cycles, multiple by 64 to get actual CPU cycles 

 SBL Initial Config Cycles - 4949178  (395.93 ms)
 SOC Init Cycles - 484851  (38.78 ms)
 DDR Config Clock Cycles - 114286  (9.14 ms)
 App Image Load Cycles - 31727948  (2538.23 ms)
 Slave Core Bootup Cycles - 14717  (1.17 ms)
 SBL Boot-up Cycles - 37293515  (2983.48 ms)
 Time at which SBL started IPU1_0 - 758468  (60.67 ms)
*****************************************************************

 Jumping to MPU CPU0 App 
[IPU1-0]     23.139480 s:  ***** IPU1_0 Firmware build time 10:31:40 Jan 28 2026 
[IPU1-0]     23.139663 s:  *** SYSTEM: CPU Frequency <ORG = 212800000 Hz>, <NEW = 212800000 Hz>
[IPU1-0]     23.217379 s:  SYSTEM: Notify register to [IPU1-1] line 0, event 15... 
[IPU1-0]     23.217562 s:  SYSTEM: Notify register to [IPU2] line 0, event 15... 
[IPU1-0]     23.217714 s:  SYSTEM: Notify register to [DSP1] line 0, event 15... 
[IPU1-0]     23.217836 s:  SYSTEM: Notify register to [HOST] line 0, event 15... 
[IPU1-0]     23.219575 s:  *** UTILS: CPU MHz = 20 Mhz ***
[IPU1-0]     23.219758 s:  SYSTEM: System Common Init in progress !!!
[IPU1-0]     23.229945 s:  UTILS: CIO: Init Done !!!
[IPU1-0]     23.230037 s:  SYSTEM: IPC init in progress !!!
[IPU1-0]     23.230128 s:  SYSTEM: Notify init done !!!
[IPU1-0]     23.231928 s:  SYSTEM: MsgQ init done !!!
[IPU1-0]     23.231989 s:  SYSTEM: IPC init DONE !!!
[IPU1-0]     23.235801 s:  SYSTEM: System Common Init Done !!!
[IPU1-0]     23.235893 s:  SYSTEM: System Init in progress !!!
[IPU1-0]     23.235954 s:  SYSTEM: BSP Common Init in progress !!!
[IPU1-0]     23.236045 s:  SYSTEM: BSP Common Init Done !!!
[IPU1-0]     23.236106 s:  SYSTEM: BSP Platform Init in progress !!!
[IPU1-0]     23.236259 s:  SYSTEM: BSP Platform Init Done !!!
[IPU1-0]     23.236381 s:  SYSTEM: FVID2 Init in progress !!!
[IPU1-0]     23.236564 s:  SYSTEM: FVID2 Init Done !!!
[IPU1-0]     23.236625 s:  SYSTEM: VPS Init in progress !!!
[IPU1-0]     23.236716 s:  SYSTEM: VPDMA Descriptor Memory Address translation ENABLED [0xa0000000 -> 0x80000000]
[IPU1-0]     23.239583 s: *** VPDMA Firmware Loading... ***
[IPU1-0]     23.239705 s: VPDMA Firmware Address = 0x9fd197c0
[IPU1-0]     23.239797 s: VPDMA Load Address     = 0x4897d004
[IPU1-0]     23.239888 s: VPDMA Firmware Version = 0x4d0001b8
[IPU1-0]     23.239980 s: VPDMA List Busy Status = 0x00000000
[IPU1-0]     23.240041 s: *** VPDMA Firmware Load Success ***
[IPU1-0]     23.240437 s: *** VPDMA Firmware Loading... ***
[IPU1-0]     23.240559 s: VPDMA Firmware Address = 0x9fd197c0
[IPU1-0]     23.240651 s: VPDMA Load Address     = 0x489dd004
[IPU1-0]     23.240743 s: VPDMA Firmware Version = 0x4d0001b8
[IPU1-0]     23.240834 s: VPDMA List Busy Status = 0x00000000
[IPU1-0]     23.240895 s: *** VPDMA Firmware Load Success ***
[IPU1-0]     23.274934 s:  SYSTEM: VPS Init Done !!!
[IPU1-0]     23.275818 s:  UTILS: DMA: HWI Create for INT34 !!!
[IPU1-0]     23.276001 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1024 
[IPU1-0]     23.276123 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 262144 B (256 KB), Free size = 257168 B (251 KB)
[IPU1-0]     23.276367 s:  SYSTEM: Heap = SR_OCMC              @ 0x00000000, Total size = 0 B (0 KB), Free size = 0 B (0 KB)
[IPU1-0]     23.276550 s:  SYSTEM: Heap = SR_DDR_CACHED        @ 0x85283000, Total size = 368037888 B (350 MB), Free size = 368037888 B (350 MB)
[IPU1-0]     23.276764 s:  SYSTEM: Heap = SR_DDR_NON_CACHED    @ 0xbfc00000, Total size = 129280 B (0 MB), Free size = 121600 B (0 MB)
[IPU1-0]     23.276916 s:  SYSTEM: Initializing Links !!! 
[IPU1-0]     23.543128 s:  SYSTEM: Initializing Links ... DONE !!! 
[IPU1-0]     23.554321 s:  BOARD: Board Init in progress !!!
[IPU1-0]     23.554718 s:  BOARD: Board Init Done !!!
[IPU1-0]     23.565942 s: 
[IPU1-0]     23.566003 s:  Vision SDK Version    : [REL_VISION_SDK_03_08_00_00]
[IPU1-0]     23.566095 s:  FVID2 Version         : [FVID_02_01_00_01]
[IPU1-0]     23.566156 s:  BSP Version           : [PDK_01_10_04__xx]
[IPU1-0]     23.566217 s:  Platform              : [EVM]
[IPU1-0]     23.566308 s:  SOC                   : [TDA2EX]
[IPU1-0]     23.566369 s:  SOC Revision          : [ES2.1]
[IPU1-0]     23.566430 s:  Board Detected        : [UNKNOWN]
[IPU1-0]     23.567864 s: 
[IPU1-0]     23.568138 s:  i2cMdSubmitChan: i2c0 transfer to slave address 0x51 failed
[IPU1-0]     23.568230 s: src/bsp_deviceI2c.c @ Line 667: 
[IPU1-0]     23.568352 s:  I2C0: DEV 0x51: ERROR !!! 
[IPU1-0]     23.568443 s: src/bsp_deviceI2c.c @ Line 689: 
[IPU1-0]     23.568504 s:  I2C0: Error timeout 1 ms!!!
[IPU1-0]     23.573415 s: 
[IPU1-0]     23.573689 s:  i2cMdSubmitChan: i2c0 transfer to slave address 0x51 failed
[IPU1-0]     23.573781 s: src/bsp_deviceI2c.c @ Line 478: 
[IPU1-0]     23.573872 s:  I2C0: DEV 0x51: RD ERROR !!!
[IPU1-0]     23.573964 s: src/bsp_deviceI2c.c @ Line 504: 
[IPU1-0]     23.574025 s:  I2C0: Error timeout 0 ms!!!
[IPU1-0]     23.574117 s: src/bsp_boardTda2ex.c @ Line 769: 
[IPU1-0]     23.574178 s: EEPROM read failed!!
[IPU1-0]     23.574239 s:  Base Board Revision   : [REV C]
[IPU1-0]     23.574330 s:  Daughter Card Revision: [REV A]
[IPU1-0]     23.574391 s:  
[IPU1-0]     23.577777 s:  SYSTEM: UART: INTERRUPT Mode is Selected 
[IPU1-1]     23.155066 s:  ***** IPU1_1 Firmware build time 10:30:09 Jan 28 2026
[IPU1-1]     23.155249 s:  *** SYSTEM: CPU Frequency <ORG = 212800000 Hz>, <NEW = 212800000 Hz>
[IPU1-1]     23.217775 s:  SYSTEM: Notify register to [IPU1-0] line 0, event 15... 
[IPU1-1]     23.217958 s:  SYSTEM: Notify register to [IPU2] line 0, event 15... 
[IPU1-1]     23.218080 s:  SYSTEM: Notify register to [DSP1] line 0, event 15... 
[IPU1-1]     23.218233 s:  SYSTEM: Notify register to [HOST] line 0, event 15... 
[IPU1-1]     23.220093 s:  SYSTEM: System Common Init in progress !!!
[IPU1-1]     23.221161 s:  UTILS: CIO: Init Done !!!
[IPU1-1]     23.221344 s:  SYSTEM: IPC init in progress !!!
[IPU1-1]     23.221435 s:  SYSTEM: Notify init done !!!
[IPU1-1]     23.223174 s:  SYSTEM: MsgQ init done !!!
[IPU1-1]     23.223327 s:  SYSTEM: IPC init DONE !!!
[IPU1-1]     23.226895 s:  SYSTEM: System Common Init Done !!!
[IPU1-1]     23.226987 s:  SYSTEM: System IPU1_1 Init in progress !!!
[IPU1-1]     23.227810 s:  UTILS: DMA: HWI Create for INT25 !!!
[IPU1-1]     23.228024 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1024 
[IPU1-1]     23.228115 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 262144 B (256 KB), Free size = 257304 B (251 KB)
[IPU1-1]     23.228329 s:  SYSTEM: Initializing Links !!! 
[IPU1-1]     23.331726 s:  UTILS: PRF: ##### Cannot allocate Object for SYNC1 ####
[IPU1-1]     23.334502 s:  UTILS: PRF: ##### Cannot allocate Object for SYNC2 ####
[IPU1-1]     23.337278 s:  UTILS: PRF: ##### Cannot allocate Object for SYNC3 ####
[IPU1-1]     23.340389 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM0 ####
[IPU1-1]     23.343652 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM1 ####
[IPU1-1]     23.346672 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM2 ####
[IPU1-1]     23.349661 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM3 ####
[IPU1-1]     23.352681 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM4 ####
[IPU1-1]     23.356402 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM5 ####
[IPU1-1]     23.359726 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM6 ####
[IPU1-1]     23.363142 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM7 ####
[IPU1-1]     23.363325 s:  SYSTEM: Initializing Links ... DONE !!! 
[IPU1-1]     23.363417 s:  SYSTEM: System IPU1_1 Init Done !!!
[HOST  ]     23.198041 s:  ***** A15_0 Firmware build time 10:29:44 Jan 28 2026 
[HOST  ]     23.198072 s:  *** SYSTEM: CPU Frequency <ORG = 588000000 Hz>, <NEW = 800000000 Hz>
[HOST  ]     23.217470 s:  SYSTEM: Notify register to [IPU1-0] line 0, event 15... 
[HOST  ]     23.217470 s:  SYSTEM: Notify register to [IPU1-1] line 0, event 15... 
[HOST  ]     23.217470 s:  SYSTEM: Notify register to [IPU2] line 0, event 15... 
[HOST  ]     23.217501 s:  SYSTEM: Notify register to [DSP1] line 0, event 15... 
[HOST  ]     23.219636 s:  SYSTEM: System Common Init in progress !!!
[HOST  ]     23.219666 s:  SYSTEM: IPC init in progress !!!
[HOST  ]     23.219666 s:  SYSTEM: Notify init done !!!
[HOST  ]     23.219727 s:  SYSTEM: MsgQ init done !!!
[HOST  ]     23.219727 s:  SYSTEM: IPC init DONE !!!
[HOST  ]     23.220246 s:  SYSTEM: System Common Init Done !!!
[HOST  ]     23.220246 s:  SYSTEM: System A15 Init in progress !!!
[HOST  ]     23.220307 s:  UTILS: DMA: HWI Create for INT66 !!!
[HOST  ]     23.220337 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1024 
[HOST  ]     23.220337 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 6291456 B (6144 KB), Free size = 6251568 B (6105 KB)
[HOST  ]     23.220368 s:  SYSTEM: Initializing Links !!! 
[HOST  ]     23.222564 s:  UTILS: PRF: ##### Cannot allocate Object for SYNC1 ####
[HOST  ]     23.222625 s:  UTILS: PRF: ##### Cannot allocate Object for SYNC2 ####
[HOST  ]     23.222686 s:  UTILS: PRF: ##### Cannot allocate Object for SYNC3 ####
[HOST  ]     23.222747 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM0 ####
[HOST  ]     23.222808 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM1 ####
[HOST  ]     23.222869 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM2 ####
[HOST  ]     23.222961 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM3 ####
[HOST  ]     23.223022 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM4 ####
[HOST  ]     23.223083 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM5 ####
[HOST  ]     23.223144 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM6 ####
[HOST  ]     23.223235 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM7 ####
[HOST  ]     23.223235 s:  SYSTEM: Initializing Links ... DONE !!! 
[HOST  ]     23.223296 s:  SYSTEM: System A15 Init Done !!!
[DSP1  ]     23.216860 s:  ***** DSP1 Firmware build time 10:30:40 Jan 28 2026
[DSP1  ]     23.216921 s:  *** SYSTEM: CPU Frequency <ORG = 600000000 Hz>, <NEW = 600000000 Hz>
[DSP1  ]     23.218050 s:  SYSTEM: Notify register to [IPU1-0] line 0, event 15... 
[DSP1  ]     23.218111 s:  SYSTEM: Notify register to [IPU1-1] line 0, event 15... 
[DSP1  ]     23.218141 s:  SYSTEM: Notify register to [IPU2] line 0, event 15... 
[DSP1  ]     23.218172 s:  SYSTEM: Notify register to [HOST] line 0, event 15... 
[DSP1  ]     23.218294 s:  *** UTILS: CPU MHz = 20 Mhz ***
[DSP1  ]     23.218355 s:  SYSTEM: System Common Init in progress !!!
[DSP1  ]     23.218507 s:  UTILS: CIO: Init Done !!!
[DSP1  ]     23.218538 s:  SYSTEM: IPC init in progress !!!
[DSP1  ]     23.218538 s:  SYSTEM: Notify init done !!!
[DSP1  ]     23.218690 s:  SYSTEM: MsgQ init done !!!
[DSP1  ]     23.218690 s:  SYSTEM: IPC init DONE !!!
[DSP1  ]     23.219392 s:  SYSTEM: System Common Init Done !!!
[DSP1  ]     23.219422 s:  SYSTEM: System DSP Init in progress !!!
[DSP1  ]     23.219605 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1024 
[DSP1  ]     23.219636 s:  SYSTEM: Heap = LOCAL_L2             @ 0x00800000, Total size = 227264 B (221 KB), Free size = 227264 B (221 KB)
[DSP1  ]     23.219666 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 524288 B (512 KB), Free size = 519464 B (507 KB)
[DSP1  ]     23.219727 s:  SYSTEM: Initializing Links !!! 
[DSP1  ]     23.227719 s:  SYSTEM: Initializing Links ... DONE !!! 
[DSP1  ]     23.227749 s: lz4CompDecomp Init
[DSP1  ]     23.227780 s:  SYSTEM: System DSP Init Done !!!
[DSP1  ]     23.552308 s:  SYSTEM: CACHE: L1P = 32 KB, L1D = 32 KB, L2 = 32 KB ... after boot !!!

What am I thinking?

(11) Base on item (9) and item (10), I think there should be no chip issues on TDA2.

(12) You already tell us, the ROM code version are the same for 26P1N8Q and 69P16CQ

(13) SBL crash in Set ABB LDO FBB mode in item (9)

(14) Base on item (10),  altough it can brings up appImage, there is still have "PMHALVMEnableABB() failed".

It seems have some problems for ABB LDO setting, but I am not sure where the root cause.

Do you have any idea to debug ABB LDO setting? Is it HW or SW issue?

Base on item (9) & (10), Why test result is different ?

Thank You

Gibbs

Hello Gibbs,

Thank you so much for the summary, this is very clear now.

I am working with the HW team to check into this. 

The fact that this works fine with other part numbers points at HW vs a SW issue but hard to say with certainty at this point. 

Are these the only two LOT codes the customer uses? Would it be possible for them to share working logs of their other devices?

-Josue

Hi, Josue

Update & Feedback,

>>Are these the only two LOT codes the customer uses? Would it be possible for them to share working logs of their other devices?

I need to discussion with customer, and need some time to wait their feedback.

This is an update.

I try to "hard code" disable any adaptive body biasing (ABB) register setting, modify as below.

pmErrCode_t PMHALVMEnableABB(pmhalPrcmVdId_t voltDomId, pmhalVmOppId_t oppId)
{
    pmErrCode_t retVal                = PM_SUCCESS;
    //uint32_t    timeout               = 0U;
    //uint32_t    intOccurred           = 0U;
    const pmhalVmVoltageDomain_t *vd  = NULL;
    const pmhalVmOppVoltage_t    *opp = NULL;

    /*
     * Check if the voltage domain id is valid and the OPP ID is valid
     * for this voltage domain.
     * PmhalVmGetVoltageDomain will return null if voltDomId is out of range.
     * PmhalVmGetOppVoltage will return null if vd is null or oppId
     * is out of range.
     */

    SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetVoltageDomai() \n");
    vd = PmhalVmGetVoltageDomain(voltDomId);

    SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetOppVoltage() \n");
    opp = PmhalVmGetOppVoltage(vd, oppId);

    if (opp == NULL)
    {
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetOppVoltage() get opp failed \n");
        retVal = PM_BADARGS;
    }
    else
    {
        /*
         * ABB Programming Overview:
         * -------------------------
         *
         * ABB LDO supports two modes, namely bypass mode and FBB mode.
         * The mode name FBB is used for historical reason but enabling
         * the FBB mode can result in Forward Body Bias (FBB) or
         * Reverse Body Bias (RBB) depending on the VSET_OUT value programmed.
         *
         * The following two registers are involved in ABB Programming:
         *
         * PRM_ABBLDO_<VD>_SETUP:
         * ----------------------
         *
         *    Bits     Field
         *    ----------------------------------------------------------------
         *     0U       SR2EN: Enable/Disable ABB power management.
         *                    This is setup as part of the ABB initialization.
         *               0x0: ABB LDO is put in bypass mode
         *               0x1: ABB is enabled
         *     1       Reserved
         *     2       ACTIVE_FBB_SEL: Defines ABB LDO mode. This is programmed
         *                             as part of enable/disable ABB.
         *               0x0: ABB LDO is in bypass mode
         *               0x1: ABB LDO is in FBB mode
         *     3       Reserved
         *     4       NO CAP: Wheter ABB LDO is cap-less or not
         *               0x0: ABB LDO uses an external capacitor
         *               0x1: ABB LDO doesn't use an external capacitor
         *     5-7     Reserved
         *     8-15    SR2_WTCNT_VALUE: LDO Settling time for active-mode OPP
         *             change. Target is 40 uSec for TDA2xx. This value is in
         *             16 system clock cycles.
         *     16-31   Reserved
         *
         * PRM_ABBLDO_<VD>_CTRL:
         * ---------------------
         *
         *    Bits     Field
         *    ----------------------------------------------------------------
         *     0U-1     OPP_SEL: Select the OPP at which the voltage domain is
         *                      operating. Only the following values are valid
         *                      for TDA2xx
         *               0x0: Nominal (default)
         *               0x1: Fast OPP
         *               0x2: Nominal
         *
         *     2       OPP_CHANGE: When set to 1, initiate an OPP-based ABBLDO
         *                         setting change
         *     3-4     SR2_STATUS: Indicate the current retVal
         *               0x0: ABB LDO is in bypass mode
         *               0x2: ABB LDO is in FBB active mode
         *     5       Reserved
         *     6       SR2_IN_TRANSITION: ABB LDO is in transition state or not
         *               0x0: Not in transition
         *               0x1: Is in transition and SR2_STATUS bits
         *                    are not stable.
         *     7-31    Reserved
         *
         * ABB Initialization:
         * -------------------
         * See PMHALVMInitABB() for details.
         *
         * NOTE: The initialization steps need to be performed only once
         *       at the system initialization; however, since we don't
         *       want to maintain state, we do the initialization every time.
         *
         * ABB Enable:
         * -----------
         *
         * To basic steps to enable ABB are:
         * 1. Set the ACTIVE_FBB_SEL bit to 1
         * 2. Set the OPP_SEL to 1 (to indicate Fast OPP)
         * 3. Program the ABB voltage in the LDOVBB<VD>_FBB_VSET_OUT field.
         * 4. Set the LDOVBB<VD>_FBB_MUX_CTRL to 1. The ABB voltage setting can
         *    be read from the efuse or the override value in the VOLTAGE_CTRL
         *    register. Setting this bit to 1 ensures the value from the
         *    VOLTAGE_CTRL register is used.
         * 5. Finally trigger the ABB LDO OPP change by setting OPP_CHANGE to 1
         *
         * Additionally the following needs to be ensured:
         * 1. Clear the ABB LDO transition completion interrupt before starting
         *    the enable sequence.
         * 2. Ensure OPP_CHANGE is zero (override if not) before setting the
         *    OPP_SEL.
         * 3. After triggering the OPP Change (step 5 above) wait for the
         *    transition to complete by checking the transition interrupt.
         */
        //uint32_t abbVsetOut = 0U;
        //uint32_t irqStatus  = 0U;

        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PMHALVMInitABB() \n");
        PMHALVMInitABB(voltDomId, oppId);

        /*
         * Clear retVal of PRCM interrupt for ABB LDO transition completion.
         */
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] Clear retVal of PRCM interrupt for ABB LDO transition completion\n");
        //HW_WR_REG32(opp->prmABBDoneIRQStatRegAddr, opp->prmABBDoneStatMask);

        /*
         * Set ABB LDO FBB mode.
         */
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] Set ABB LDO FBB mode\n");
        //HW_WR_FIELD32(opp->prmABBLDOSetupRegAddr,
        //              PRM_ABBLDO_DSPEVE_SETUP_ACTIVE_FBB_SEL,
        //              PRM_ABBLDO_DSPEVE_SETUP_ACTIVE_FBB_SEL_FBB);

        /*
         * Ensure OPP_CHANGE is set to 0U and set OPP_SEL to Fast OPP.
         */
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] Ensure OPP_CHANGE is set to 0U and set OPP_SEL to Fast OPP\n");
        //HW_WR_FIELD32(opp->prmABBLDOCtrlRegAddr,
        //              PRM_ABBLDO_DSPEVE_CTRL_OPP_CHANGE,
        //              0x0U);
        //HW_WR_FIELD32(opp->prmABBLDOCtrlRegAddr, PRM_ABBLDO_DSPEVE_CTRL_OPP_SEL,
        //              PRM_ABBLDO_DSPEVE_CTRL_OPP_SEL_FASTOPP);

        /*
         * Read the ABB VSET value from the efuse and set the
         * LDOVBBxxxVSET_OUT filed in the register
         * CTRL_<CORE|WKUP>_LDOVBB_<domain>_VOLTAGE_CTRL.
         * Also ensure that this override VSET value is used by setting the
         * MUX.
         */

        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] Read the ABB VSET value from the efuse\n");

        HW_RD_FIELD32(opp->fuseOPPVminRegAddr,
                                   PMHAL_VM_STD_FUSE_OPP_VMIN_VSETABB);


        //abbVsetOut = HW_RD_FIELD32(opp->fuseOPPVminRegAddr,
        //                           PMHAL_VM_STD_FUSE_OPP_VMIN_VSETABB);

        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] Read the abbVsetOut\n");

        //HW_WR_FIELD32(opp->ctrlLDOVBBVoltageCtrlRegAddr,
        //              PMHAL_VM_LDOVBB_VOLTAGE_CTRL_FBB_VSET_OUT,
        //              abbVsetOut);

        //HW_WR_FIELD32(
        //    opp->ctrlLDOVBBVoltageCtrlRegAddr,
        //    PMHAL_VM_LDOVBB_VOLTAGE_CTRL_FBB_MUX_CTRL,
        //    PMHAL_VM_LDOVBB_VOLTAGE_CTRL_FBB_MUX_CTRL_OCP);

        /*
         * Start the ABB LDO OPP Change.
         */
        //HW_WR_FIELD32(opp->prmABBLDOCtrlRegAddr,
        //              PRM_ABBLDO_DSPEVE_CTRL_OPP_CHANGE, 0x1U);

        /*
         * Wait till the transition is complete by checking the DONE bit.
         * The transition takes 50us; use 100us timeout delay to gives some
         * buffer.
         */
        //timeout     = 100U;
        //intOccurred = 0U;
        //while ((intOccurred == 0U) && (timeout != 0U))
        //{
        //    PMUtilsMinDelayUS((uint32_t) 1U);
        //    intOccurred = HW_RD_REG32(opp->prmABBDoneIRQStatRegAddr) &
        //                  opp->prmABBDoneStatMask;
        //    timeout = timeout - 1U;
        //}

        //if (timeout == 0U)
        //{
        //    SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PM_TIMEOUT\n");
            retVal = PM_TIMEOUT;
        //}

        /*
         * Clear interrupt retVal.
         */
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] Clear interrupt retVal\n");
        //irqStatus  = HW_RD_REG32(opp->prmABBDoneIRQStatRegAddr);
        //irqStatus |= opp->prmABBDoneStatMask;
        //HW_WR_REG32(opp->prmABBDoneIRQStatRegAddr, irqStatus);
    }

    return retVal;

}

and then SBL can run to load appImage, log as below.

SBL finish boot procedure even we still have errors with ABB setting.

This is SD BOOT.

Welcome to minicom 2.7.1

OPTIONS: I18n 
Compiled on Dec 23 2019, 02:06:26.
Port /dev/ttyUSB0, 17:29:55

Press CTRL-A Z for help on special keys

�����
[Gibbs][sbl_tda2ex_main.c] TDA2EX UART1_INST INIT

[Gibbs][sbl_tda2ex_main.c] This project is define SOC_TDA2EX

[Gibbs][sbl_tda2ex_main.c] sblBuildMode = SBLLIB_SBL_BUILD_MODE_DEV

[Gibbs][sbl_tda2ex_main.c] ARM_CCNT_Enable, reset PMU CLOCK counter

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId()

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId not define SOC_TDA2XX

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId, oppId = SBLLIB_PRCM_DPLL_OPP_NOM

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] Enter SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex_17x17

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->PMHALI2CCommRegister()

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17 

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->pmicOps = PMHALLP8733GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733ConfigureRegulatorMap()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733IsPresent()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetVendorId()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetProductId()

[Gibbs][sbl_utils_tda2xx.c] PMHALPmicRegister() ok

[Gibbs][sbl_utils_tda2xx.c] Get the VD rail info based on the current board

[Gibbs][sbl_utils_tda2xx.c] defined SOC_TDA2EX

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17 

[Gibbs][sbl_utils_tda2xx.c] In SBLUtilsConfigAllVoltageRails()->vdInfoObj = &vdInfo_tda2ex_17x17

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[0].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[1].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[2].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[3].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[4].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] ENTER_11

[Gibbs][sbl_utils_tda2xx.c] ENTER_12

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_15

[Gibbs][sbl_utils_tda2xx.c] ENTER_16

[Gibbs][sbl_utils_tda2xx.c] enter SblUtilsConfigGangedVdRails()

[Gibbs][sbl_utils_tda2xx.c] configOpp = PMHAL_VM_OPP_NOM

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][pmhal_vm.c] pmhalVmGetOppVoltage() start

[Gibbs][pmhal_vm.c] PMHALVMGetAVS0EfuseVoltage() ok 

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][pmhal_vm.c] PPMHALVMGetCurrentVoltage() ok 

[Gibbs][pmhal_vm.c] isABBSupported == TRUE 

[Gibbs][pmhal_vm.c] PMHALPmicSetRegulatorVoltage() 

[Gibbs][pmhal_lp8733.c] PMHALLP8733SetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PMHALLP8733EnableRegulator()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VoltageToVselOffset()

[Gibbs][pmhal_lp8733.c] PmhalLP8733WritePhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][sbl_utils_tda2xx.c] PPMHALVMSetOpp() success

[Gibbs][sbl_utils_tda2xx.c]PMHALVMEnableABB() start

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetVoltageDomai() 

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetOppVoltage() 

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PMHALVMInitABB() 

[Gibbs][pmhal_vm.c] Clear retVal of PRCM interrupt for ABB LDO transition completion

[Gibbs][pmhal_vm.c] Set ABB LDO FBB mode

[Gibbs][pmhal_vm.c] Ensure OPP_CHANGE is set to 0U and set OPP_SEL to Fast OPP

[Gibbs][pmhal_vm.c] Read the ABB VSET value from the efuse

[Gibbs][pmhal_vm.c] Read the abbVsetOut

[Gibbs][pmhal_vm.c] Clear interrupt retVal

[Gibbs][sbl_utils_tda2xx.c] PMHALVMEnableABB failed, break

[Gibbs][sbl_utils_tda2xx.c] ENTER_17

[Gibbs][sbl_utils_tda2xx.c] SblUtilsConfigGangedVdRails failed

[Gibbs][sbl_utils_tda2xx.c] In SBLUtilsConfigAllVoltageRails()->SblUtilsMMCSDLdoPowerOn()

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails failed

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigPowerDomains() ok

[Gibbs][sbl_tda2ex_main.c] SSBLLibUnlockControlModuleMMR()

[Gibbs][sbl_tda2ex_main.c] Intc_Init()

[Gibbs][sbl_tda2ex_main.c] Intc_IntEnable()

[Gibbs][sbl_tda2ex_main.c] SBLUtilsWDTimerBegin()

[Gibbs][sbl_tda2ex_main.c] SBLLibGetDpllStructure() ok

[Gibbs][sbl_tda2ex_main.c] PMHALCMMuxParentSelect()

[Gibbs][sbl_tda2ex_main.c] PMHALCMDpllConfigure() ok

�Cࡅ[Gibbs][sbl_tda2ex_main.c] PMHALCMDpllConfigure() ok

[Gibbs][sbl_tda2ex_main.c] TDA2Ex SBL Boot 

[Gibbs][sbl_tda2ex_main.c] SBLLibHSOpenL3Firewalls()

 [Gibbs][sbl_tda2ex_main.c] SBL Initial Config Failed 

[Gibbs][sbl_tda2ex_main.c] Configure DPLLS

 DPLL Configuration Completed 

[Gibbs][sbl_tda2ex_main.c] Configure CLOCK DOMAINS

 Clock Domain Configuration Completed 

[Gibbs][sbl_tda2ex_main.c] Configure CLOCK MODULES

 Module Enable Configuration Completed 

[Gibbs][sbl_tda2ex_main.c] Configure SBLConfigTIEVMPad()

 TI EVM PAD Config Completed 

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigStaticDependency() ok

[Gibbs][sbl_tda2ex_main.c] Configure SBLUtilsDDR3Config()

 DDR Config Completed 

[Gibbs][sbl_tda2ex_main.c] Initialize the EDMA

[Gibbs][sbl_tda2ex_main.c] Reset the slave cores 

[Gibbs][sbl_tda2ex_main.c] App Image Download Begins 

 SD Boot - file open completed successfully 

 MPU CPU0 Image Load Completed 

 IPU1 CPU0 Image Load Completed 

 IPU1 CPU1 Image Load Completed 

 IPU2 CPU0 and CPU1 Image Load Completed 

 DSP1 Image Load Completed 

 App Image Download Completed 

*****************************************************************

 PMCCNTR counts once every 64 clock cycles, multiple by 64 to get actual CPU cycles 

 SBL Initial Config Cycles - 4870104  (389.60 ms)
 SOC Init Cycles - 479470  (38.35 ms)
 DDR Config Clock Cycles - 113899  (9.11 ms)
 App Image Load Cycles - 29395853  (2351.66 ms)
 Slave Core Bootup Cycles - 14193  (1.13 ms)
 SBL Boot-up Cycles - 34874635  (2789.97 ms)
 Time at which SBL started IPU1_0 - 106444  (8.51 ms)
*****************************************************************

 Jumping to MPU CPU0 App 
[IPU1-0]      3.252211 s:  ***** IPU1_0 Firmware build time 10:31:40 Jan 28 2026 
[IPU1-0]      3.252394 s:  *** SYSTEM: CPU Frequency <ORG = 212800000 Hz>, <NEW = 212800000 Hz>
[IPU1-0]      3.330293 s:  SYSTEM: Notify register to [IPU1-1] line 0, event 15... 
[IPU1-0]      3.330476 s:  SYSTEM: Notify register to [IPU2] line 0, event 15... 
[IPU1-0]      3.330628 s:  SYSTEM: Notify register to [DSP1] line 0, event 15... 
[IPU1-0]      3.330750 s:  SYSTEM: Notify register to [HOST] line 0, event 15... 
[IPU1-0]      3.332489 s:  *** UTILS: CPU MHz = 20 Mhz ***
[IPU1-0]      3.332672 s:  SYSTEM: System Common Init in progress !!!
[IPU1-0]      3.342737 s:  UTILS: CIO: Init Done !!!
[IPU1-0]      3.342859 s:  SYSTEM: IPC init in progress !!!
[IPU1-0]      3.342920 s:  SYSTEM: Notify init done !!!
[IPU1-0]      3.344720 s:  SYSTEM: MsgQ init done !!!
[IPU1-0]      3.344781 s:  SYSTEM: IPC init DONE !!!
[IPU1-0]      3.348593 s:  SYSTEM: System Common Init Done !!!
[IPU1-0]      3.348685 s:  SYSTEM: System Init in progress !!!
[IPU1-0]      3.348746 s:  SYSTEM: BSP Common Init in progress !!!
[IPU1-0]      3.348807 s:  SYSTEM: BSP Common Init Done !!!
[IPU1-0]      3.348898 s:  SYSTEM: BSP Platform Init in progress !!!
[IPU1-0]      3.349020 s:  SYSTEM: BSP Platform Init Done !!!
[IPU1-0]      3.349112 s:  SYSTEM: FVID2 Init in progress !!!
[IPU1-0]      3.349325 s:  SYSTEM: FVID2 Init Done !!!
[IPU1-0]      3.349417 s:  SYSTEM: VPS Init in progress !!!
[IPU1-0]      3.349478 s:  SYSTEM: VPDMA Descriptor Memory Address translation ENABLED [0xa0000000 -> 0x80000000]
[IPU1-0]      3.352345 s: *** VPDMA Firmware Loading... ***
[IPU1-0]      3.352467 s: VPDMA Firmware Address = 0x9fd197c0
[IPU1-0]      3.352528 s: VPDMA Load Address     = 0x4897d004
[IPU1-0]      3.352650 s: VPDMA Firmware Version = 0x4d0001b8
[IPU1-0]      3.352711 s: VPDMA List Busy Status = 0x00000000
[IPU1-0]      3.352803 s: *** VPDMA Firmware Load Success ***
[IPU1-0]      3.353138 s: *** VPDMA Firmware Loading... ***
[IPU1-0]      3.353291 s: VPDMA Firmware Address = 0x9fd197c0
[IPU1-0]      3.353382 s: VPDMA Load Address     = 0x489dd004
[IPU1-0]      3.353504 s: VPDMA Firmware Version = 0x4d0001b8
[IPU1-0]      3.353565 s: VPDMA List Busy Status = 0x00000000
[IPU1-0]      3.353657 s: *** VPDMA Firmware Load Success ***
[IPU1-0]      3.387482 s:  SYSTEM: VPS Init Done !!!
[IPU1-0]      3.388366 s:  UTILS: DMA: HWI Create for INT34 !!!
[IPU1-0]      3.388549 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1024 
[IPU1-0]      3.388641 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 262144 B (256 KB), Free size = 257168 B (251 KB)
[IPU1-0]      3.388824 s:  SYSTEM: Heap = SR_OCMC              @ 0x00000000, Total size = 0 B (0 KB), Free size = 0 B (0 KB)
[IPU1-0]      3.389007 s:  SYSTEM: Heap = SR_DDR_CACHED        @ 0x85283000, Total size = 368037888 B (350 MB), Free size = 368037888 B (350 MB)
[IPU1-0]      3.389221 s:  SYSTEM: Heap = SR_DDR_NON_CACHED    @ 0xbfc00000, Total size = 129280 B (0 MB), Free size = 121600 B (0 MB)
[IPU1-0]      3.389434 s:  SYSTEM: Initializing Links !!! 
[IPU1-0]      3.654974 s:  SYSTEM: Initializing Links ... DONE !!! 
[IPU1-0]      3.665253 s:  BOARD: Board Init in progress !!!
[IPU1-0]      3.665649 s:  BOARD: Board Init Done !!!
[IPU1-0]      3.676874 s: 
[IPU1-0]      3.676935 s:  Vision SDK Version    : [REL_VISION_SDK_03_08_00_00]
[IPU1-0]      3.677026 s:  FVID2 Version         : [FVID_02_01_00_01]
[IPU1-0]      3.677087 s:  BSP Version           : [PDK_01_10_04__xx]
[IPU1-0]      3.677148 s:  Platform              : [EVM]
[IPU1-0]      3.677209 s:  SOC                   : [TDA2EX]
[IPU1-0]      3.677301 s:  SOC Revision          : [ES2.1]
[IPU1-0]      3.677362 s:  Board Detected        : [UNKNOWN]
[IPU1-0]      3.678765 s: 
[IPU1-0]      3.679039 s:  i2cMdSubmitChan: i2c0 transfer to slave address 0x51 failed
[IPU1-0]      3.679161 s: src/bsp_deviceI2c.c @ Line 667: 
[IPU1-0]      3.679253 s:  I2C0: DEV 0x51: ERROR !!! 
[IPU1-0]      3.679344 s: src/bsp_deviceI2c.c @ Line 689: 
[IPU1-0]      3.679405 s:  I2C0: Error timeout 1 ms!!!
[IPU1-0]      3.684346 s: 
[IPU1-0]      3.684621 s:  i2cMdSubmitChan: i2c0 transfer to slave address 0x51 failed
[IPU1-0]      3.684743 s: src/bsp_deviceI2c.c @ Line 478: 
[IPU1-0]      3.684804 s:  I2C0: DEV 0x51: RD ERROR !!!
[IPU1-0]      3.684895 s: src/bsp_deviceI2c.c @ Line 504: 
[IPU1-0]      3.684956 s:  I2C0: Error timeout 1 ms!!!
[IPU1-0]      3.685048 s: src/bsp_boardTda2ex.c @ Line 769: 
[IPU1-0]      3.685109 s: EEPROM read failed!!
[IPU1-0]      3.685170 s:  Base Board Revision   : [REV C]
[IPU1-0]      3.685262 s:  Daughter Card Revision: [REV A]
[IPU1-0]      3.685323 s:  
[IPU1-0]      3.688708 s:  SYSTEM: UART: INTERRUPT Mode is Selected 
[IPU1-1]      3.267797 s:  ***** IPU1_1 Firmware build time 10:30:09 Jan 28 2026
[IPU1-1]      3.267980 s:  *** SYSTEM: CPU Frequency <ORG = 212800000 Hz>, <NEW = 212800000 Hz>
[IPU1-1]      3.330720 s:  SYSTEM: Notify register to [IPU1-0] line 0, event 15... 
[IPU1-1]      3.330872 s:  SYSTEM: Notify register to [IPU2] line 0, event 15... 
[IPU1-1]      3.331025 s:  SYSTEM: Notify register to [DSP1] line 0, event 15... 
[IPU1-1]      3.331147 s:  SYSTEM: Notify register to [HOST] line 0, event 15... 
[IPU1-1]      3.333007 s:  SYSTEM: System Common Init in progress !!!
[IPU1-1]      3.334075 s:  UTILS: CIO: Init Done !!!
[IPU1-1]      3.334197 s:  SYSTEM: IPC init in progress !!!
[IPU1-1]      3.334319 s:  SYSTEM: Notify init done !!!
[IPU1-1]      3.336058 s:  SYSTEM: MsgQ init done !!!
[IPU1-1]      3.336180 s:  SYSTEM: IPC init DONE !!!
[IPU1-1]      3.339748 s:  SYSTEM: System Common Init Done !!!
[IPU1-1]      3.339840 s:  SYSTEM: System IPU1_1 Init in progress !!!
[IPU1-1]      3.340663 s:  UTILS: DMA: HWI Create for INT25 !!!
[IPU1-1]      3.340877 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1024 
[IPU1-1]      3.340968 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 262144 B (256 KB), Free size = 257304 B (251 KB)
[IPU1-1]      3.341121 s:  SYSTEM: Initializing Links !!! 
[IPU1-1]      3.444030 s:  UTILS: PRF: ##### Cannot allocate Object for SYNC1 ####
[IPU1-1]      3.446776 s:  UTILS: PRF: ##### Cannot allocate Object for SYNC2 ####
[IPU1-1]      3.449582 s:  UTILS: PRF: ##### Cannot allocate Object for SYNC3 ####
[IPU1-1]      3.452784 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM0 ####
[IPU1-1]      3.455926 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM1 ####
[IPU1-1]      3.458915 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM2 ####
[IPU1-1]      3.461812 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM3 ####
[IPU1-1]      3.464741 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM4 ####
[IPU1-1]      3.467943 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM5 ####
[IPU1-1]      3.471542 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM6 ####
[IPU1-1]      3.474958 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM7 ####
[IPU1-1]      3.475080 s:  SYSTEM: Initializing Links ... DONE !!! 
[IPU1-1]      3.475172 s:  SYSTEM: System IPU1_1 Init Done !!!
[HOST  ]      3.309705 s:  ***** A15_0 Firmware build time 10:29:44 Jan 28 2026 
[HOST  ]      3.309735 s:  *** SYSTEM: CPU Frequency <ORG = 588000000 Hz>, <NEW = 800000000 Hz>
[HOST  ]      3.330384 s:  SYSTEM: Notify register to [IPU1-0] line 0, event 15... 
[HOST  ]      3.330384 s:  SYSTEM: Notify register to [IPU1-1] line 0, event 15... 
[HOST  ]      3.330415 s:  SYSTEM: Notify register to [IPU2] line 0, event 15... 
[HOST  ]      3.330415 s:  SYSTEM: Notify register to [DSP1] line 0, event 15... 
[HOST  ]      3.332550 s:  SYSTEM: System Common Init in progress !!!
[HOST  ]      3.332580 s:  SYSTEM: IPC init in progress !!!
[HOST  ]      3.332580 s:  SYSTEM: Notify init done !!!
[HOST  ]      3.332641 s:  SYSTEM: MsgQ init done !!!
[HOST  ]      3.332641 s:  SYSTEM: IPC init DONE !!!
[HOST  ]      3.333160 s:  SYSTEM: System Common Init Done !!!
[HOST  ]      3.333160 s:  SYSTEM: System A15 Init in progress !!!
[HOST  ]      3.333221 s:  UTILS: DMA: HWI Create for INT66 !!!
[HOST  ]      3.333221 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1024 
[HOST  ]      3.333251 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 6291456 B (6144 KB), Free size = 6251568 B (6105 KB)
[HOST  ]      3.333282 s:  SYSTEM: Initializing Links !!! 
[HOST  ]      3.335478 s:  UTILS: PRF: ##### Cannot allocate Object for SYNC1 ####
[HOST  ]      3.335539 s:  UTILS: PRF: ##### Cannot allocate Object for SYNC2 ####
[HOST  ]      3.335600 s:  UTILS: PRF: ##### Cannot allocate Object for SYNC3 ####
[HOST  ]      3.335661 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM0 ####
[HOST  ]      3.335722 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM1 ####
[HOST  ]      3.335783 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM2 ####
[HOST  ]      3.335844 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM3 ####
[HOST  ]      3.335936 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM4 ####
[HOST  ]      3.335997 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM5 ####
[HOST  ]      3.336058 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM6 ####
[HOST  ]      3.336119 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM7 ####
[HOST  ]      3.336149 s:  SYSTEM: Initializing Links ... DONE !!! 
[HOST  ]      3.336180 s:  SYSTEM: System A15 Init Done !!!
[DSP1  ]      3.329805 s:  ***** DSP1 Firmware build time 10:30:40 Jan 28 2026
[DSP1  ]      3.329866 s:  *** SYSTEM: CPU Frequency <ORG = 600000000 Hz>, <NEW = 600000000 Hz>
[DSP1  ]      3.330964 s:  SYSTEM: Notify register to [IPU1-0] line 0, event 15... 
[DSP1  ]      3.331025 s:  SYSTEM: Notify register to [IPU1-1] line 0, event 15... 
[DSP1  ]      3.331055 s:  SYSTEM: Notify register to [IPU2] line 0, event 15... 
[DSP1  ]      3.331086 s:  SYSTEM: Notify register to [HOST] line 0, event 15... 
[DSP1  ]      3.331238 s:  *** UTILS: CPU MHz = 20 Mhz ***
[DSP1  ]      3.331269 s:  SYSTEM: System Common Init in progress !!!
[DSP1  ]      3.331421 s:  UTILS: CIO: Init Done !!!
[DSP1  ]      3.331452 s:  SYSTEM: IPC init in progress !!!
[DSP1  ]      3.331482 s:  SYSTEM: Notify init done !!!
[DSP1  ]      3.331604 s:  SYSTEM: MsgQ init done !!!
[DSP1  ]      3.331635 s:  SYSTEM: IPC init DONE !!!
[DSP1  ]      3.332306 s:  SYSTEM: System Common Init Done !!!
[DSP1  ]      3.332336 s:  SYSTEM: System DSP Init in progress !!!
[DSP1  ]      3.332519 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1024 
[DSP1  ]      3.332550 s:  SYSTEM: Heap = LOCAL_L2             @ 0x00800000, Total size = 227264 B (221 KB), Free size = 227264 B (221 KB)
[DSP1  ]      3.332580 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 524288 B (512 KB), Free size = 519464 B (507 KB)
[DSP1  ]      3.332641 s:  SYSTEM: Initializing Links !!! 
[DSP1  ]      3.340633 s:  SYSTEM: Initializing Links ... DONE !!! 
[DSP1  ]      3.340663 s: lz4CompDecomp Init
[DSP1  ]      3.340694 s:  SYSTEM: System DSP Init Done !!!
[DSP1  ]      3.664246 s:  SYSTEM: CACHE: L1P = 32 KB, L1D = 32 KB, L2 = 32 KB ... after boot !!!
[DSP1  ]      3.664277 s:  SYSTEM: CACHE: L1P = 32 KB, L1D = 32 KB, L2 = 32 KB ... after update by APP !!!
[IPU2  ]      3.250076 s:  ***** IPU2 Firmware build time 10:31:42 Jan 28 2026
[IPU2  ]      3.250259 s:  *** SYSTEM: CPU Frequency <ORG = 212800000 Hz>, <NEW = 212800000 Hz>
[IPU2  ]      3.330964 s:  SYSTEM: Notify register to [IPU1-0] line 0, event 15... 
[IPU2  ]      3.331116 s:  SYSTEM: Notify register to [IPU1-1] line 0, event 15... 
[IPU2  ]      3.331238 s:  SYSTEM: Notify register to [DSP1] line 0, event 15... 
[IPU2  ]      3.331330 s:  SYSTEM: Notify register to [HOST] line 0, event 15... 
[IPU2  ]      3.333923 s:  SYSTEM: System Common Init in progress !!!
[IPU2  ]      3.335082 s:  UTILS: CIO: Init Done !!!
[IPU2  ]      3.335204 s:  SYSTEM: IPC init in progress !!!
[IPU2  ]      3.335295 s:  SYSTEM: Notify init done !!!
[IPU2  ]      3.337034 s:  SYSTEM: MsgQ init done !!!
[IPU2  ]      3.337125 s:  SYSTEM: IPC init DONE !!!
[IPU2  ]      3.342280 s:  SYSTEM: System Common Init Done !!!
[IPU2  ]      3.342402 s:  SYSTEM: System IPU2 Init in progress !!!
[IPU2  ]      3.343134 s:  UTILS: DMA: HWI Create for INT25 !!!
[IPU2  ]      3.343378 s:  SYSTEM: SW Message Box Msg Pool, Free Msg Count = 1024 
[IPU2  ]      3.343500 s:  SYSTEM: Heap = LOCAL_DDR            @ 0x00000000, Total size = 262144 B (256 KB), Free size = 257256 B (251 KB)
[IPU2  ]      3.343652 s:  SYSTEM: Initializing Links !!! 
[IPU2  ]      3.444091 s:  UTILS: PRF: ##### Cannot allocate Object for SYNC1 ####
[IPU2  ]      3.446806 s:  UTILS: PRF: ##### Cannot allocate Object for SYNC2 ####
[IPU2  ]      3.449521 s:  UTILS: PRF: ##### Cannot allocate Object for SYNC3 ####
[IPU2  ]      3.452327 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM0 ####
[IPU2  ]      3.455102 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM1 ####
[IPU2  ]      3.457969 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM2 ####
[IPU2  ]      3.460836 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM3 ####
[IPU2  ]      3.463704 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM4 ####
[IPU2  ]      3.466601 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM5 ####
[IPU2  ]      3.469529 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM6 ####
[IPU2  ]      3.472457 s:  UTILS: PRF: ##### Cannot allocate Object for ALGORITHM7 ####
[IPU2  ]      3.472610 s:  SYSTEM: Initializing Links ... DONE !!! 
[IPU2  ]      3.472671 s:  SYSTEM: System IPU2 Init Done !!!
[IPU1-0]      4.692734 s:  QSPI Init Started 
[IPU1-0]      4.692948 s:  MID - 0 
[IPU1-0]      4.693009 s:  DID - 0 
[IPU1-0]      4.693039 s:  QSPI Init Completed Sucessfully 
[IPU1-0]      4.706368 s:  
[IPU1-0]      4.706429 s:  Current System Settings,
[IPU1-0]      4.706460 s:  ========================
[IPU1-0]      4.706521 s:  Display Type   : HDMI 1920x1080 @ 60fps 
[IPU1-0]      4.706582 s:  Capture Source : Sensor OV10635 1280x720  @ 30fps - VIP, YUV422 
[IPU1-0]      4.706673 s:  My IP address for interface 1 : 0.0.0.0 
[IPU1-0]      4.706734 s:  My IP address for interface 2 : 0.0.0.0 
[IPU1-0]      4.706795 s:  ISS Settings   : LDC=[OFF] VTNF=[OFF] WDR=[OFF] 
[IPU1-0]      4.706887 s:  
[IPU1-0]      4.706917 s:  ============
[IPU1-0]      4.706948 s:  Usecase Menu
[IPU1-0]      4.707009 s:  ============
[IPU1-0]      4.707039 s: 
[IPU1-0]  
[IPU1-0]  Vision SDK Usecases,
[IPU1-0]  -------------------- 
[IPU1-0]  1: Single Camera Usecases
[IPU1-0]  2: Multi-Camera LVDS Usecases
[IPU1-0]  3: AVB RX Usecases, (TDA2x & TDA2Ex ONLY)
[IPU1-0]  4: Dual Display Usecases, (TDA2x EVM ONLY)
[IPU1-0]  5: ISS Usecases, (TDA3x ONLY)
[IPU1-0]  6: TDA2x Stereo Usecases 
[IPU1-0]  7: Network RX/TX Usecases
[IPU1-0]  9: RADAR Usecases
[IPU1-0]  a: Miscellaneous test's
[IPU1-0]  f: TIDL Usecase
[IPU1-0]  g: Camera Radar Combo Usecases
[IPU1-0]  
[IPU1-0]  s: System Settings 
[IPU1-0]  
[IPU1-0]  x: Exit 
[IPU1-0]  
[IPU1-0]  Enter Choice: 
[IPU1-0]  
[HOST  ]      8.335600 s:  NETWORK_CTRL: Starting Server (port=5000) !!!
[HOST  ]      8.335631 s:  NETWORK_CTRL: Starting Server ... DONE (port=5000) !!!

My question.

(1) Base on my test result, I think the issue should be very clear. Why SBL crash in ABB register setting? (ex:HW_WR_FIELD32)

(2) Is it necessary to enable ABB for TDA2EG-17?  

Need you provide debug suggestion.

Thank You.

Gibbs

Hello Gibbs,

I will confer with our teams and report back.

What is the failure rate? 100% of this LOT code only? 1-2 devices?

-Josue

Hello Gibbs,

Still waiting on some feedback from you above:

1. Josue Zamitiz-Ayala said:

   What is the failure rate? 100% of this LOT code only? 1-2 devices?

• Josue Zamitiz-Ayala said:

  Are these the only two LOT codes the customer uses? Would it be possible for them to share working logs of their other devices?

Anyhow, I've heard back from the HW team and ABB can be disabled. 

Can you compare the following once you have a working sample:

Can you compare these registers:

The ABB LDO target value can be read from CTRL_CORE_STD_FUSE_OPP_VMIN_xxx_y[24:20] VSETABB bits, if  CTRL_CORE_STD_FUSE_OPP_VMIN_xxx_y[25] ABBEN is set to 0x1.

ABBEN defines whether ABB should be used and this is dependent upon the specific OPP and voltage domain.

-Josue

Hello Josue.

This is an update that I found (replies) in this week.

Q1/A1 : What is the failure rate? 100% of this LOT code only? 

Feed back from customer

Here are failed LOT code SoC : 89P16CQ / 36P11VQ / 26P1RLQ / 26P1N8Q * 4 PCS

Build 7 PCS, all of them boot failed. so far, I do not see any boot failed reason with specific LOT code. 

Q2/A2 : Can you compare the following once you have a working sample

So we use same SBL "w/ ABB enable" binary, the only different is that one runs on "old board", and another runs on "new board".

"new board" have boot failed issue

Old & new board almost have the same schematic deign and layout, but the different is that new board remove eMMC/OSPI flash.

Old board log:

[Gibbs][sbl_tda2ex_main.c] TDA2EX UART1_INST INIT

[Gibbs][sbl_tda2ex_main.c] This project is define SOC_TDA2EX

[Gibbs][sbl_tda2ex_main.c] sblBuildMode = SBLLIB_SBL_BUILD_MODE_DEV

[Gibbs][sbl_tda2ex_main.c] ARM_CCNT_Enable, reset PMU CLOCK counter

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId()

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId not define SOC_TDA2XX

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId, oppId = SBLLIB_PRCM_DPLL_OPP                                                                 _NOM

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] Enter SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex                                                                 _17x17

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->PMHALI2CCommRegiste                                                                 r()

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->pmicOps = PMHALLP87                                                                 33GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733ConfigureRegulatorMap()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733IsPresent()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetVendorId()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetProductId()

[Gibbs][sbl_utils_tda2xx.c] PMHALPmicRegister() ok

[Gibbs][sbl_utils_tda2xx.c] Get the VD rail info based on the current board

[Gibbs][sbl_utils_tda2xx.c] defined SOC_TDA2EX

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17

[Gibbs][sbl_utils_tda2xx.c] In SBLUtilsConfigAllVoltageRails()->vdInfoObj = &vdI                                                                 nfo_tda2ex_17x17

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[0].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[1].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[2].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[3].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[4].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] ENTER_11

[Gibbs][sbl_utils_tda2xx.c] ENTER_12

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_15

[Gibbs][sbl_utils_tda2xx.c] ENTER_16

[Gibbs][sbl_utils_tda2xx.c] enter SblUtilsConfigGangedVdRails()

[Gibbs][sbl_utils_tda2xx.c] configOpp = PMHAL_VM_OPP_NOM

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][pmhal_vm.c] pmhalVmGetOppVoltage() start

[Gibbs][pmhal_vm.c] PMHALVMGetAVS0EfuseVoltage() ok

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][pmhal_vm.c] PPMHALVMGetCurrentVoltage() ok

[Gibbs][pmhal_vm.c] isABBSupported == false

[Gibbs][pmhal_vm.c] PMHALPmicSetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PMHALLP8733SetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PMHALLP8733EnableRegulator()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VoltageToVselOffset()

[Gibbs][pmhal_lp8733.c] PmhalLP8733WritePhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][sbl_utils_tda2xx.c] PPMHALVMSetOpp() success

[Gibbs][sbl_utils_tda2xx.c]PMHALVMEnableABB() start

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetVoltageDomai()

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetOppVoltage()

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PMHALVMInitABB()

[Gibbs][pmhal_vm.c] Clear retVal of PRCM interrupt for ABB LDO transition comple                                                                 tion

[Gibbs][pmhal_vm.c] Set ABB LDO FBB mode

[Gibbs][pmhal_vm.c] Ensure OPP_CHANGE is set to 0U and set OPP_SEL to Fast OPP

[Gibbs][pmhal_vm.c] Read the ABB VSET value from the efuse

[Gibbs][pmhal_vm.c] Read the abbVsetOut

[Gibbs][pmhal_vm.c] Clear interrupt retVal

[Gibbs][sbl_utils_tda2xx.c]PMHALVMEnableABB() start

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetVoltageDomai()

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetOppVoltage()

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PMHALVMInitABB()

[Gibbs][pmhal_vm.c] Clear retVal of PRCM interrupt for ABB LDO transition comple                                                                 tion

[Gibbs][pmhal_vm.c] Set ABB LDO FBB mode

[Gibbs][pmhal_vm.c] Ensure OPP_CHANGE is set to 0U and set OPP_SEL to Fast OPP

[Gibbs][pmhal_vm.c] Read the ABB VSET value from the efuse

[Gibbs][pmhal_vm.c] Read the abbVsetOut

[Gibbs][pmhal_vm.c] Clear interrupt retVal

[Gibbs][sbl_utils_tda2xx.c] ENTER_17

[Gibbs][sbl_utils_tda2xx.c] SblUtilsConfigGangedVdRails success

[Gibbs][sbl_utils_tda2xx.c] ENTER_12

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_15

[Gibbs][sbl_utils_tda2xx.c] ENTER_16

[Gibbs][sbl_utils_tda2xx.c] enter SblUtilsConfigGangedVdRails()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][pmhal_vm.c] pmhalVmGetOppVoltage() start

[Gibbs][pmhal_vm.c] PMHALVMGetAVS0EfuseVoltage() ok

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][pmhal_vm.c] PPMHALVMGetCurrentVoltage() ok

[Gibbs][pmhal_vm.c] isABBSupported == TRUE

[Gibbs][pmhal_vm.c] PMHALPmicSetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PMHALLP8733SetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PMHALLP8733EnableRegulator()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VoltageToVselOffset()

[Gibbs][pmhal_lp8733.c] PmhalLP8733WritePhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][pmhal_vm.c] PPMHALVMEnableABB()

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetVoltageDomai()

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetOppVoltage()

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PMHALVMInitABB()

[Gibbs][pmhal_vm.c] Clear retVal of PRCM interrupt for ABB LDO transition comple                                                                 tion

[Gibbs][pmhal_vm.c] Set ABB LDO FBB mode

[Gibbs][pmhal_vm.c] Ensure OPP_CHANGE is set to 0U and set OPP_SEL to Fast OPP

[Gibbs][pmhal_vm.c] Read the ABB VSET value from the efuse

[Gibbs][pmhal_vm.c] Read the abbVsetOut

[Gibbs][pmhal_vm.c] Clear interrupt retVal

[Gibbs][sbl_utils_tda2xx.c] PPMHALVMSetOpp() success

[Gibbs][sbl_utils_tda2xx.c]PMHALVMEnableABB() start

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetVoltageDomai()

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetOppVoltage()

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PMHALVMInitABB()

[Gibbs][pmhal_vm.c] Clear retVal of PRCM interrupt for ABB LDO transition comple                                                                 tion

[Gibbs][pmhal_vm.c] Set ABB LDO FBB mode

[Gibbs][pmhal_vm.c] Ensure OPP_CHANGE is set to 0U and set OPP_SEL to Fast OPP

[Gibbs][pmhal_vm.c] Read the ABB VSET value from the efuse

[Gibbs][pmhal_vm.c] Read the abbVsetOut

[Gibbs][pmhal_vm.c] Clear interrupt retVal

[Gibbs][sbl_utils_tda2xx.c] ENTER_17

[Gibbs][sbl_utils_tda2xx.c] SblUtilsConfigGangedVdRails success

[Gibbs][sbl_utils_tda2xx.c] In SBLUtilsConfigAllVoltageRails()->SblUtilsMMCSDLdo                                                                 PowerOn()

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails SUCCESS

[Gibbs][sbl_tda2xx_priv.c] SBLGetBootMode() = SBLLIB_BOOT_MODE_SD

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigPowerDomains() ok

[Gibbs][sbl_tda2ex_main.c] SSBLLibUnlockControlModuleMMR()

[Gibbs][sbl_tda2ex_main.c] Intc_Init()

[Gibbs][sbl_tda2ex_main.c] Intc_IntEnable()

[Gibbs][sbl_tda2ex_main.c] SBLUtilsWDTimerBegin()

[Gibbs][sbl_tda2ex_main.c] SBLLibGetDpllStructure() ok

[Gibbs][sbl_tda2ex_main.c] PMHALCMMuxParentSelect()

[Gibbs][sbl_tda2ex_main.c] PMHALCMDpllConfigure() ok

 C [Gibbs][sbl_tda2ex_main.c] PMHALCMDpllConfigure() ok

[Gibbs][sbl_tda2ex_main.c] TDA2Ex SBL Boot

[Gibbs][sbl_tda2ex_main.c] SBLLibHSOpenL3Firewalls()

 [Gibbs][sbl_tda2ex_main.c] SBL Initial Success

[Gibbs][sbl_tda2ex_main.c] Configure DPLLS

 DPLL Configuration Completed

[Gibbs][sbl_tda2ex_main.c] Configure CLOCK DOMAINS

 Clock Domain Configuration Completed

[Gibbs][sbl_tda2ex_main.c] Configure CLOCK MODULES

 Module Enable Configuration Completed

[Gibbs][sbl_tda2ex_main.c] Configure SBLConfigTIEVMPad()

 TI EVM PAD Config Completed

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigStaticDependency() ok

[Gibbs][sbl_tda2ex_main.c] Configure SBLUtilsDDR3Config()

 DDR Config Completed

[Gibbs][sbl_tda2ex_main.c] Initialize the EDMA

[Gibbs][sbl_tda2ex_main.c] Reset the slave cores

[Gibbs][sbl_tda2ex_main.c] App Image Download Begins

 SD Boot - file open completed successfully

 MPU CPU0 Image Load Completed

 IPU1 CPU0 Image Load Completed

 IPU1 CPU1 Image Load Completed

 IPU2 CPU0 and CPU1 Image Load Completed

 DSP1 Image Load Completed

 App Image Download Completed

*****************************************************************

 PMCCNTR counts once every 64 clock cycles, multiple by 64 to get actual CPU cyc                                                                 les

 SBL Initial Config Cycles - 8164971  (653.19 ms)
 SOC Init Cycles - 479689  (38.37 ms)
 DDR Config Clock Cycles - 113574  (9.8 ms)
 App Image Load Cycles - 23261244  (1860.89 ms)
 Slave Core Bootup Cycles - 14299  (1.14 ms)
 SBL Boot-up Cycles - 32034858  (2562.78 ms)
 Time at which SBL started IPU1_0 - 102421  (8.19 ms)
*****************************************************************

 Jumping to MPU CPU0 App
[IPU1-0]      3.129506 s:  ***** IPU1_0 Firmware build time 15:55:19 Jan  2 2026                                                                 
[IPU1-0]      3.129689 s:  *** SYSTEM: CPU Frequency <ORG = 212800000 Hz>, <NEW                                                                  = 212800000 Hz>
[IPU1-0]      3.188983 s:  SYSTEM: Notify register to [IPU1-1] line 0, event 15.                                                                 ..
[IPU1-0]      3.189166 s:  SYSTEM: Notify register to [IPU2] line 0, event 15...                                                                 
[IPU1-0]      3.189257 s:  SYSTEM: Notify register to [DSP1] line 0, event 15...                                                                 
[IPU1-0]      3.189379 s:  SYSTEM: Notify register to [HOST] line 0, event 15...

New board log. (Failed in set ABB)

Welcome to minicom 2.7.1

OPTIONS: I18n 
Compiled on Dec 23 2019, 02:06:26.
Port /dev/ttyUSB0, 10:48:47

Press CTRL-A Z for help on special keys


[Gibbs][sbl_tda2ex_main.c] TDA2EX UART1_INST INIT

[Gibbs][sbl_tda2ex_main.c] This project is define SOC_TDA2EX

[Gibbs][sbl_tda2ex_main.c] sblBuildMode = SBLLIB_SBL_BUILD_MODE_DEV

[Gibbs][sbl_tda2ex_main.c] ARM_CCNT_Enable, reset PMU CLOCK counter

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId()

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId not define SOC_TDA2XX

[Gibbs][sbl_tda2xx_priv.c] In function SBLGetOppId, oppId = SBLLIB_PRCM_DPLL_OPP_NOM

[Gibbs][sbl_tda2ex_main.c] SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] Enter SBLUtilsConfigAllVoltageRails()

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->stuff vdInfo_tda2ex_17x17

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->PMHALI2CCommRegister()

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17 

[Gibbs][sbl_utils_tda2xx.c] SBLUtilsConfigAllVoltageRails()->pmicOps = PMHALLP8733GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733ConfigureRegulatorMap()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetPMICOps()

[Gibbs][pmhal_lp8733.c] PMHALLP8733IsPresent()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetVendorId()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetProductId()

[Gibbs][sbl_utils_tda2xx.c] PMHALPmicRegister() ok

[Gibbs][sbl_utils_tda2xx.c] Get the VD rail info based on the current board

[Gibbs][sbl_utils_tda2xx.c] defined SOC_TDA2EX

[Gibbs][sbl_utils_tda2xx.c] detect silicon is ACKAGE_TYPE_17X17 

[Gibbs][sbl_utils_tda2xx.c] In SBLUtilsConfigAllVoltageRails()->vdInfoObj = &vdInfo_tda2ex_17x17

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[0].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[1].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[2].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[3].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] In for loop configure vdInfoObj[4].gangId

[Gibbs][sbl_utils_tda2xx.c] retVal = PM_SUCCESS

[Gibbs][sbl_utils_tda2xx.c] ENTER_11

[Gibbs][sbl_utils_tda2xx.c] ENTER_12

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_13

[Gibbs][sbl_utils_tda2xx.c] ENTER_14

[Gibbs][sbl_utils_tda2xx.c] ENTER_15

[Gibbs][sbl_utils_tda2xx.c] ENTER_16

[Gibbs][sbl_utils_tda2xx.c] enter SblUtilsConfigGangedVdRails()

[Gibbs][sbl_utils_tda2xx.c] configOpp = PMHAL_VM_OPP_NOM

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][sbl_utils_tda2xx.c] PMHALVMGetAVS0EfuseVoltage()

[Gibbs][pmhal_vm.c] pmhalVmGetOppVoltage() start

[Gibbs][pmhal_vm.c] PMHALVMGetAVS0EfuseVoltage() ok 

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][pmhal_vm.c] PPMHALVMGetCurrentVoltage() ok 

[Gibbs][pmhal_vm.c] isABBSupported == TRUE 

[Gibbs][pmhal_vm.c] PMHALPmicSetRegulatorVoltage() 

[Gibbs][pmhal_lp8733.c] PMHALLP8733SetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PMHALLP8733EnableRegulator()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VoltageToVselOffset()

[Gibbs][pmhal_lp8733.c] PmhalLP8733WritePhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][pmhal_lp8733.c] PMHALLP8733GetRegulatorVoltage()

[Gibbs][pmhal_lp8733.c] PPmhalLP8733CheckRegulatorEnabled()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733ReadPhyAddr()

[Gibbs][pmhal_lp8733.c] PmhalLP8733VselOffsetToVoltage()

[Gibbs][sbl_utils_tda2xx.c] PPMHALVMSetOpp() success

[Gibbs][sbl_utils_tda2xx.c]PMHALVMEnableABB() start

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetVoltageDomai() 

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetOppVoltage() 

[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PMHALVMInitABB() 

[Gibbs][pmhal_vm.c] Clear retVal of PRCM interrupt for ABB LDO transition completion

[Gibbs][pmhal_vm.c] Set ABB LDO FBB mode

We found old board detect "ABB support = false", so I guess that's why it can boot success.

New board detect "ABB support = true", so I that is why  boot crash happens when ABB enable.

So far I do not have idea why SBL detect ABB support is true.

/* =============================================================================
 *   Copyright (c) Texas Instruments Incorporated 2014
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

/**
 * \file pmhal_vm.c
 *
 * \brief   Voltage Manager API implementation.
 *
 *          The Voltage API supports the following features:
 *          - Operating Performance Point (OPP)
 *          - AVS Class-0U
 *          - Adaptive Body Bias (ABB)
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

#include <stdint.h>
#include <stddef.h>
#include <ti/csl/soc.h>
#include <ti/csl/hw_types.h>
#include "pm_types.h"
#include "pm_utils.h"
#include "pmhal_prcm.h"
#include "pmhal_pmic.h"
#include "pmhal_vm.h"
#include "pmhal_cm.h"
#include "hw_pmhal_vmdata.h"
#include "hw_pmhal_data.h"
#include "common/hw_pmhal_common_vmdata.h"

//Gibbs
#include <ti/boot/sbl_auto/sbl_lib/sbl_lib.h>
#include <ti/boot/sbl_auto/sbl_lib/sbl_lib_board.h>
#include <ti/boot/sbl_auto/sbl_lib/sbl_lib_config.h>
#include <ti/boot/sbl_auto/sbl_utils/sbl_utils_tda2xx.h>
#include <ti/boot/sbl_auto/sbl_utils/sbl_utils_common.h>

/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */

/* None */

/* ========================================================================== */
/*                         Structures and Enums                               */
/* ========================================================================== */

/* None */

/* ========================================================================== */
/*                 Internal Function Declarations                             */
/* ========================================================================== */

/**
 * \brief Calculate the wait count (WTCNT) value. This value determines
 *        the duration ABB LDO waits to get to the target voltage. This
 *        value is in number of system clock cycles.
 *
 * \param  None
 *
 * \return Return the WTCNT value in units of 16 sys_clk cycles.
 *
 */
static uint32_t PmhalVmGetWtCnt(void);

/**
 * \brief Read the package type and determine the index of the voltage to choose
 *        in the VM database.
 *
 * \param  None
 *
 * \return nomVoltageIndex  Index of the  voltage to choose
 *                          in the VM database.
 *
 */
static uint32_t PmhalVmGetVoltageIndex(void);

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

/* None */

/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */

pmErrCode_t PMHALVMSetOpp(pmhalPrcmVdId_t voltDomId, pmhalVmOppId_t oppId,
                          uint32_t timeout)
{
    pmErrCode_t retVal = PM_SUCCESS;
    const pmhalVmVoltageDomain_t    *vd         = NULL;
    const pmhalVmOppVoltage_t       *oppVoltage = NULL;
    uint32_t    volt_mv         = 0U;
    uint32_t    isABBEnable     = 0U;
    uint32_t    curr_mv         = 0U;

    /*
     * Check if the voltage domain id is valid and the OPP ID is valid
     * for this voltage domain.
     * PmhalVmGetVoltageDomain will return null if voltDomId is out of range.
     * PmhalVmGetOppVoltage will return null if vd is null or oppId
     * is out of range.
     */
    vd = PmhalVmGetVoltageDomain(voltDomId);
    if (NULL == vd)
    {
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PmhalVmGetVoltageDomain() return null\n");
        retVal = PM_INPUT_PARAM_BAD_VOLTAGE_ID;
    }
    else
    {
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] pmhalVmGetOppVoltage() start\n");
        oppVoltage = PmhalVmGetOppVoltage(vd, oppId);
        if (oppVoltage == NULL)
        {
            SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] return failed\n");
            retVal = PM_BADARGS;
        }
    }

    if (PM_SUCCESS == retVal)
    {
        /*
         * Get the AVS Class-0U voltage to be used.
         */
        volt_mv = PMHALVMGetAVS0EfuseVoltage(voltDomId, oppId);

        if (volt_mv != 0U)
        {

            SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PMHALVMGetAVS0EfuseVoltage() ok \n");

            /*
            * Get the current value of the voltage rail.
            * This will be used to compare against the desired voltage.
            * If the rail is already configured for this exact voltage setting
            * there is no need to again set the voltage.
            */
            retVal = PMHALVMGetCurrentVoltage(voltDomId, &curr_mv);

            /*
             * Nothing to be done if the current voltage rail is the same
             * as the desired voltage.
             */
            if ((retVal == PM_SUCCESS) && (curr_mv != volt_mv))
            {
                SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PPMHALVMGetCurrentVoltage() ok \n");

                /*
                 * ABB Programming Overview:
                 * -------------------------
                 *
                 * ABB LDO supports two modes, namely bypass mode and
                 * FBB mode. The mode name FBB is used for historical
                 * reason but enabling the FBB mode can result in
                 * Forward Body Bias (FBB) or Reverse Body Bias (RBB)
                 * depending on the VSET_OUT value programmed.
                 *
                 * When changing OPP, if the old OPP required ABB then,
                 * we need to disable (put ABB LDO in bypass mode),
                 * change the voltage and if the new OPP requires ABB,
                 * enable ABB.
                 *
                 * The ABB first needs to be initialized.
                 * See PMHALVMInitABB() for details.
                 *
                 * NOTE: The initialization steps need to be performed
                 *       only once at the system initialization;
                 *       however, since we don't want to maintain
                 *       state, we do the initialization every time.
                 *
                 * The Setup and Control registers to program ABB
                 * are described in PMHALVMEnableABB().
                 *
                 * NOTE: The oppVoltage structure represents the
                 *       new OPP we need to enter into; however, we need
                 *       to check if the current OPPrequired ABB. Since
                 *       the same control/retVal registers are used for
                 *       a given VD, we can use the new OPP structure
                 *       to check if the current OPP required ABB.
                 */

                pmhalPrcmPmicRegulatorId_t regId = PmhalVmGetRegulatorId(
                    voltDomId);

                if (oppVoltage->isABBSupported == TRUE)
                {
                    uint32_t vminAbbEn;

                    SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] isABBSupported == TRUE \n");

                    PMHALVMInitABB(voltDomId, oppId);
                    isABBEnable = (uint32_t) PMHALVMIsABBEnabled(voltDomId,
                                                                 oppId);
                    if (isABBEnable == TRUE)
                    {
                        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PMHALVMDisableABB() \n");
                        retVal = PMHALVMDisableABB(voltDomId, oppId);
                    }

                    if (PM_SUCCESS == retVal)
                    {
                        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PMHALPmicSetRegulatorVoltage() \n");
                        retVal = PMHALPmicSetRegulatorVoltage(regId, volt_mv,
                                                              timeout,
                                                              (uint32_t) TRUE);
                    }
                    if (PM_SUCCESS == retVal)
                    {
                        vminAbbEn =
                            HW_RD_FIELD32(oppVoltage->fuseOPPVminRegAddr,
                                          PMHAL_VM_STD_FUSE_OPP_VMIN_ABBEN);

                        if (vminAbbEn != 0U)
                        {
                            SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PPMHALVMEnableABB() \n");
                            retVal = PMHALVMEnableABB(voltDomId, oppId);
                        }
                    }
                }
                else
                {
                    SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] isABBSupported == false \n");
                    SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PMHALPmicSetRegulatorVoltage() \n");
                    retVal = PMHALPmicSetRegulatorVoltage(regId, volt_mv,
                                                          timeout,
                                                          (uint32_t) TRUE);
                }
            }
        }
        else
        {
            retVal = PM_VOLTAGE_INVALID;
        }
    }

    return retVal;
}

pmErrCode_t PMHALVMGetCurrentVoltage(pmhalPrcmVdId_t voltDomId,
                                     uint32_t       *voltage)
{
    pmErrCode_t retVal = PM_SUCCESS;

    /*
     * Check the input parameters.
     */
    if ((voltage == NULL) ||
        ((voltDomId >= PMHAL_PRCM_VD_COUNT) || (voltDomId < PMHAL_PRCM_VD_MIN)))
    {
        retVal = PM_BADARGS;
    }
    else
    {
        /*
         * Get the voltage regulator ID and query the PMIC to get the
         * voltage setting from that regulator.
         */
        pmhalPrcmPmicRegulatorId_t regId = PmhalVmGetRegulatorId(voltDomId);
        /*
         * Set the default voltage value. If any error conditions
         * occurs the value of voltage = 0U is given back to the caller.
         */
        *voltage = 0U;
        retVal   = PMHALPmicGetRegulatorVoltage(regId, voltage);
    }

    return retVal;
}

pmErrCode_t PMHALVMGetCurrentOpp(pmhalPrcmVdId_t voltDomId,
                                 pmhalVmOppId_t *oppId)
{
    pmErrCode_t retVal = PM_SUCCESS;
    const pmhalVmVoltageDomain_t *vd = NULL;
    uint32_t    voltage    = 0U;
    uint32_t    done       = FALSE;
    uint32_t    avsVoltage = 0U;
    const pmhalVmOppVoltage_t    *opp = NULL;
    int32_t     i;
    uint32_t    nomVoltageIndex = 0U;

    if ((voltDomId >= PMHAL_PRCM_VD_COUNT) || (oppId == NULL))
    {
        retVal = PM_BADARGS;
    }
    else
    {
        retVal = PMHALVMGetCurrentVoltage(voltDomId, &voltage);
        vd     = PmhalVmGetVoltageDomain(voltDomId);

        if (NULL != vd)
        {
            if (PM_SUCCESS == retVal)
            {
                nomVoltageIndex = PmhalVmGetVoltageIndex();

                /*
                 * Scan through all the OPPs of a given voltage domain and
                 * find the OPP for which the voltage matches the current
                 * voltage.
                 */
                for (i = PMHAL_VM_OPP_MIN;
                     ((FALSE == done) && (i < PMHAL_VM_OPP_MAX)); i++)
                {
                    opp = PmhalVmGetOppVoltage(vd, (uint32_t) i);
                    if (opp != NULL)
                    {
                        /* Check if voltage = boot voltage */
                        if (voltage == opp->nomVoltage[nomVoltageIndex])
                        {
                            *oppId = (pmhalVmOppId_t) vd->oppIdArr[i];
                            done   = TRUE;
                        }
                        else
                        {
                            avsVoltage = 0U;
                            if (opp->isAVSSupported == TRUE)
                            {
                                pmhalPrcmPmicRegulatorId_t regId =
                                    PmhalVmGetRegulatorId(voltDomId);
                                uint32_t checkVoltage;

                                avsVoltage = PMHALVMGetAVS0EfuseVoltage(
                                    voltDomId,
                                    (pmhalVmOppId_t) i);
                                checkVoltage =
                                    PMHALPmicGetConvRegulatorVoltage(regId,
                                                                     avsVoltage);
                                if (checkVoltage == voltage)
                                {
                                    *oppId = (pmhalVmOppId_t) vd->oppIdArr[i];
                                    done   = TRUE;
                                }
                            }
                        }
                    }
                }

                /*
                 * At system start-up, AVS may not be enabled so the above code
                 * will fail to find the OPP. Make a last attempt to check
                 * against the OPP_NOM range to see if it matches.
                 */
                if ((FALSE == done) &&
                    (voltage >= vd->minOppNommV) &&
                    (voltage <= vd->maxOppNommV))
                {
                    *oppId = (pmhalVmOppId_t) PMHAL_VM_OPP_NOM;
                    done   = TRUE;
                }
            }
        }
    }

    if ((PM_SUCCESS == retVal) && (FALSE == done))
    {
        retVal = PM_OPP_INVALID;
    }

    return retVal;
}

uint32_t PMHALVMGetAVS0EfuseVoltage(pmhalPrcmVdId_t voltDomId,
                                    pmhalVmOppId_t  oppId)
{
    pmErrCode_t retVal = PM_SUCCESS;
    uint32_t voltage = 0U; /* Initialize with error value */
    uint32_t nomVoltageIndex = 0U;
    const pmhalVmVoltageDomain_t *vd         = NULL;
    const pmhalVmOppVoltage_t    *oppVoltage = NULL;

    /*
     * Check if the voltage domain id is valid and the OPP ID is valid
     * for this voltage domain.
     * PmhalVmGetVoltageDomain will return null if voltDomId is out of range.
     * PmhalVmGetOppVoltage will return null if vd is null or oppId
     * is out of range.
     */
    vd = PmhalVmGetVoltageDomain(voltDomId);
    if (NULL == vd)
    {
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PmhalVmGetVoltageDomain() return vd = null\n");
        retVal = PM_INPUT_PARAM_BAD_VOLTAGE_ID;
    }
    else
    {
        oppVoltage = PmhalVmGetOppVoltage(vd, oppId);
        if (oppVoltage == NULL)
        {
            SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PmhalVmGetVoltageDomain() return oppVoltage = NULL\n");
            retVal = PM_BADARGS;
        }
    }

    /*
     * Make sure AVS is supported
     */
    if ((retVal == PM_SUCCESS) &&
        (oppVoltage != NULL)   &&
        (oppVoltage->isAVSSupported == 1U))
    {
        voltage = HW_RD_FIELD32(oppVoltage->fuseOPPVminRegAddr,
                                PMHAL_VM_STD_FUSE_OPP_VMIN_AVS0);
        /*
         * Some devices may not support all of the listed OPPs and
         * therefore will not have any value populated in the eFuse. In these
         * cases 0x0000 or 0xFFFF may be expected. This helper function returns
         * a 0U in such cases to be handled by the API appropriately.
         */
        if ((voltage == 0U) || (voltage == 0xFFFU))
        {
            SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PMHAL_VM_STD_FUSE_OPP_VMIN_AVS0 return 0 or 0xfffu\n");

            nomVoltageIndex = PmhalVmGetVoltageIndex();
            if(oppVoltage->nomVoltage[nomVoltageIndex] != 0U)
            {
                /*
                 * If AVS Class-0U is not supported, use the Voltage
                 * from the OPP table if a valid nomVoltage is present.
                 */
                voltage = oppVoltage->nomVoltage[nomVoltageIndex];
            }
            else
            {
                /*
                 * If AVS is not supported for the given OPP and there is no
                 * valid nom voltage defined then returns 0U.
                 */
                voltage = 0U;
            }
        }

        /*
         * Make sure the voltage value is with-in the limits for the
         * voltage domain.
         */
        if ((voltage < vd->minSafemV) || (voltage > vd->maxSafemV))
        {
            SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] < vd->minSafemV or vd->maxSafemV\n");

            voltage = 0U;
        }
    }
    else
    {
        voltage = 0U;
    }

    return voltage;
}

uint32_t PMHALVMIsABBEnabled(pmhalPrcmVdId_t voltDomId, pmhalVmOppId_t oppId)
{
    uint32_t fbbSel, oppSel;
    uint32_t retVal = 0U;
    const pmhalVmVoltageDomain_t *vd         = NULL;
    const pmhalVmOppVoltage_t    *oppVoltage = NULL;

    /*
     * Check if the voltage domain id is valid and the OPP ID is valid
     * for this voltage domain.
     * PmhalVmGetVoltageDomain will return null if voltDomId is out of range.
     * PmhalVmGetOppVoltage will return null if vd is null or oppId
     * is out of range.
     */
    vd = PmhalVmGetVoltageDomain(voltDomId);

    oppVoltage = PmhalVmGetOppVoltage(vd, oppId);

    if (oppVoltage != NULL)
    {
        fbbSel = HW_RD_FIELD32(oppVoltage->prmABBLDOSetupRegAddr,
                               PRM_ABBLDO_DSPEVE_SETUP_ACTIVE_FBB_SEL);
        oppSel = HW_RD_FIELD32(oppVoltage->prmABBLDOCtrlRegAddr,
                               PRM_ABBLDO_DSPEVE_CTRL_OPP_SEL);

        if ((fbbSel != 0U) && (oppSel != 0U))
        {
            retVal = 1U;
        }
        else
        {
            retVal = 0U;
        }
    }

    return retVal;
}

void PMHALVMInitABB(pmhalPrcmVdId_t voltDomId, pmhalVmOppId_t oppId)
{
    uint32_t wtcnt;
    uint32_t setupValue = 0U;
    const pmhalVmVoltageDomain_t *vd  = NULL;
    const pmhalVmOppVoltage_t    *opp = NULL;

    /*
     * Check if the voltage domain id is valid and the OPP ID is valid
     * for this voltage domain.
     * PmhalVmGetVoltageDomain will return null if voltDomId is out of range.
     * PmhalVmGetOppVoltage will return null if vd is null or oppId
     * is out of range.
     */
    vd = PmhalVmGetVoltageDomain(voltDomId);

    opp = PmhalVmGetOppVoltage(vd, oppId);

    /*
     * The following ABB initialization steps are required to use ABB:
     * 1. Set up the WTCNT value (see PmhalVmGetWtCnt() for details)
     * 2. Set PRM_ABBLDO_<VD>_SETUP.SR2EN to 1
     * 3. Initialize PRM_ABBLDO_<VD>_SETUP.ACTIVE_FBB_SEL to 0U. This will
     *    be programmed as needed by the OPP change.
     * 4. Ensure PRM_ABBLDO_<VD>_SETUP.NOCAP is unchanged from reset value.
     *    This value is automatically loaded.
     * 5. Ensure all other bits are zero.
     */
    if ((opp != NULL) && (opp->prmABBLDOSetupRegAddr != 0U))
    {
        /*
         * Read the NOCAP bits and retain its value; clear all other bits.
         */
        setupValue  = HW_RD_REG32(opp->prmABBLDOSetupRegAddr);
        setupValue &= PRM_ABBLDO_DSPEVE_SETUP_NOCAP_MASK;

        /*
         * Set WTCNT and SR2EN fields and write the register value.
         */
        wtcnt       = PmhalVmGetWtCnt();
        setupValue |= wtcnt << PRM_ABBLDO_DSPEVE_SETUP_SR2_WTCNT_VALUE_SHIFT;
        setupValue |= (uint32_t) PRM_ABBLDO_DSPEVE_SETUP_SR2EN_FUNCTIONAL <<
                      PRM_ABBLDO_DSPEVE_SETUP_SR2EN_SHIFT;
        HW_WR_REG32(opp->prmABBLDOSetupRegAddr, setupValue);
    }
}

pmErrCode_t PMHALVMEnableABB(pmhalPrcmVdId_t voltDomId, pmhalVmOppId_t oppId)
{
    pmErrCode_t retVal                = PM_SUCCESS;
    uint32_t    timeout               = 0U;
    uint32_t    intOccurred           = 0U;
    const pmhalVmVoltageDomain_t *vd  = NULL;
    const pmhalVmOppVoltage_t    *opp = NULL;

    /*
     * Check if the voltage domain id is valid and the OPP ID is valid
     * for this voltage domain.
     * PmhalVmGetVoltageDomain will return null if voltDomId is out of range.
     * PmhalVmGetOppVoltage will return null if vd is null or oppId
     * is out of range.
     */

    SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetVoltageDomai() \n");
    vd = PmhalVmGetVoltageDomain(voltDomId);

    SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetOppVoltage() \n");
    opp = PmhalVmGetOppVoltage(vd, oppId);

    if (opp == NULL)
    {
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PmhalVmGetOppVoltage() get opp failed \n");
        retVal = PM_BADARGS;
    }
    else
    {
        /*
         * ABB Programming Overview:
         * -------------------------
         *
         * ABB LDO supports two modes, namely bypass mode and FBB mode.
         * The mode name FBB is used for historical reason but enabling
         * the FBB mode can result in Forward Body Bias (FBB) or
         * Reverse Body Bias (RBB) depending on the VSET_OUT value programmed.
         *
         * The following two registers are involved in ABB Programming:
         *
         * PRM_ABBLDO_<VD>_SETUP:
         * ----------------------
         *
         *    Bits     Field
         *    ----------------------------------------------------------------
         *     0U       SR2EN: Enable/Disable ABB power management.
         *                    This is setup as part of the ABB initialization.
         *               0x0: ABB LDO is put in bypass mode
         *               0x1: ABB is enabled
         *     1       Reserved
         *     2       ACTIVE_FBB_SEL: Defines ABB LDO mode. This is programmed
         *                             as part of enable/disable ABB.
         *               0x0: ABB LDO is in bypass mode
         *               0x1: ABB LDO is in FBB mode
         *     3       Reserved
         *     4       NO CAP: Wheter ABB LDO is cap-less or not
         *               0x0: ABB LDO uses an external capacitor
         *               0x1: ABB LDO doesn't use an external capacitor
         *     5-7     Reserved
         *     8-15    SR2_WTCNT_VALUE: LDO Settling time for active-mode OPP
         *             change. Target is 40 uSec for TDA2xx. This value is in
         *             16 system clock cycles.
         *     16-31   Reserved
         *
         * PRM_ABBLDO_<VD>_CTRL:
         * ---------------------
         *
         *    Bits     Field
         *    ----------------------------------------------------------------
         *     0U-1     OPP_SEL: Select the OPP at which the voltage domain is
         *                      operating. Only the following values are valid
         *                      for TDA2xx
         *               0x0: Nominal (default)
         *               0x1: Fast OPP
         *               0x2: Nominal
         *
         *     2       OPP_CHANGE: When set to 1, initiate an OPP-based ABBLDO
         *                         setting change
         *     3-4     SR2_STATUS: Indicate the current retVal
         *               0x0: ABB LDO is in bypass mode
         *               0x2: ABB LDO is in FBB active mode
         *     5       Reserved
         *     6       SR2_IN_TRANSITION: ABB LDO is in transition state or not
         *               0x0: Not in transition
         *               0x1: Is in transition and SR2_STATUS bits
         *                    are not stable.
         *     7-31    Reserved
         *
         * ABB Initialization:
         * -------------------
         * See PMHALVMInitABB() for details.
         *
         * NOTE: The initialization steps need to be performed only once
         *       at the system initialization; however, since we don't
         *       want to maintain state, we do the initialization every time.
         *
         * ABB Enable:
         * -----------
         *
         * To basic steps to enable ABB are:
         * 1. Set the ACTIVE_FBB_SEL bit to 1
         * 2. Set the OPP_SEL to 1 (to indicate Fast OPP)
         * 3. Program the ABB voltage in the LDOVBB<VD>_FBB_VSET_OUT field.
         * 4. Set the LDOVBB<VD>_FBB_MUX_CTRL to 1. The ABB voltage setting can
         *    be read from the efuse or the override value in the VOLTAGE_CTRL
         *    register. Setting this bit to 1 ensures the value from the
         *    VOLTAGE_CTRL register is used.
         * 5. Finally trigger the ABB LDO OPP change by setting OPP_CHANGE to 1
         *
         * Additionally the following needs to be ensured:
         * 1. Clear the ABB LDO transition completion interrupt before starting
         *    the enable sequence.
         * 2. Ensure OPP_CHANGE is zero (override if not) before setting the
         *    OPP_SEL.
         * 3. After triggering the OPP Change (step 5 above) wait for the
         *    transition to complete by checking the transition interrupt.
         */
        uint32_t abbVsetOut = 0U;
        uint32_t irqStatus  = 0U;

        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PMHALVMEnableABB() -> PMHALVMInitABB() \n");
        PMHALVMInitABB(voltDomId, oppId);

        /*
         * Clear retVal of PRCM interrupt for ABB LDO transition completion.
         */
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] Clear retVal of PRCM interrupt for ABB LDO transition completion\n");
        HW_WR_REG32(opp->prmABBDoneIRQStatRegAddr, opp->prmABBDoneStatMask);

        /*
         * Set ABB LDO FBB mode.
         */
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] Set ABB LDO FBB mode\n");
        HW_WR_FIELD32(opp->prmABBLDOSetupRegAddr,
                      PRM_ABBLDO_DSPEVE_SETUP_ACTIVE_FBB_SEL,
                      PRM_ABBLDO_DSPEVE_SETUP_ACTIVE_FBB_SEL_FBB);

        /*
         * Ensure OPP_CHANGE is set to 0U and set OPP_SEL to Fast OPP.
         */
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] Ensure OPP_CHANGE is set to 0U and set OPP_SEL to Fast OPP\n");
        HW_WR_FIELD32(opp->prmABBLDOCtrlRegAddr,
                      PRM_ABBLDO_DSPEVE_CTRL_OPP_CHANGE,
                      0x0U);
        HW_WR_FIELD32(opp->prmABBLDOCtrlRegAddr, PRM_ABBLDO_DSPEVE_CTRL_OPP_SEL,
                      PRM_ABBLDO_DSPEVE_CTRL_OPP_SEL_FASTOPP);

        /*
         * Read the ABB VSET value from the efuse and set the
         * LDOVBBxxxVSET_OUT filed in the register
         * CTRL_<CORE|WKUP>_LDOVBB_<domain>_VOLTAGE_CTRL.
         * Also ensure that this override VSET value is used by setting the
         * MUX.
         */

        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] Read the ABB VSET value from the efuse\n");

        HW_RD_FIELD32(opp->fuseOPPVminRegAddr,
                                   PMHAL_VM_STD_FUSE_OPP_VMIN_VSETABB);


        abbVsetOut = HW_RD_FIELD32(opp->fuseOPPVminRegAddr,
                                   PMHAL_VM_STD_FUSE_OPP_VMIN_VSETABB);

        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] Read the abbVsetOut\n");

        HW_WR_FIELD32(opp->ctrlLDOVBBVoltageCtrlRegAddr,
                      PMHAL_VM_LDOVBB_VOLTAGE_CTRL_FBB_VSET_OUT,
                      abbVsetOut);

        HW_WR_FIELD32(
            opp->ctrlLDOVBBVoltageCtrlRegAddr,
            PMHAL_VM_LDOVBB_VOLTAGE_CTRL_FBB_MUX_CTRL,
            PMHAL_VM_LDOVBB_VOLTAGE_CTRL_FBB_MUX_CTRL_OCP);

        /*
         * Start the ABB LDO OPP Change.
         */
        HW_WR_FIELD32(opp->prmABBLDOCtrlRegAddr,
                      PRM_ABBLDO_DSPEVE_CTRL_OPP_CHANGE, 0x1U);

        /*
         * Wait till the transition is complete by checking the DONE bit.
         * The transition takes 50us; use 100us timeout delay to gives some
         * buffer.
         */
        timeout     = 100U;
        intOccurred = 0U;
        while ((intOccurred == 0U) && (timeout != 0U))
        {
            PMUtilsMinDelayUS((uint32_t) 1U);
            intOccurred = HW_RD_REG32(opp->prmABBDoneIRQStatRegAddr) &
                          opp->prmABBDoneStatMask;
            timeout = timeout - 1U;
        }

        if (timeout == 0U)
        {
            SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PM_TIMEOUT\n");
            retVal = PM_TIMEOUT;
        }

        /*
         * Clear interrupt retVal.
         */
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] Clear interrupt retVal\n");
        irqStatus  = HW_RD_REG32(opp->prmABBDoneIRQStatRegAddr);
        irqStatus |= opp->prmABBDoneStatMask;
        HW_WR_REG32(opp->prmABBDoneIRQStatRegAddr, irqStatus);
    }

    return retVal;

}

pmErrCode_t PMHALVMDisableABB(pmhalPrcmVdId_t voltDomId, pmhalVmOppId_t oppId)
{
    pmErrCode_t retVal                = PM_SUCCESS;
    uint32_t    timeout               = 0U;
    uint32_t    intOccurred           = 0U;
    const pmhalVmVoltageDomain_t *vd  = NULL;
    const pmhalVmOppVoltage_t    *opp = NULL;

    /*
     * Check if the voltage domain id is valid and the OPP ID is valid
     * for this voltage domain.
     * PmhalVmGetVoltageDomain will return null if voltDomId is out of range.
     * PmhalVmGetOppVoltage will return null if vd is null or oppId
     * is out of range.
     */
    vd = PmhalVmGetVoltageDomain(voltDomId);

    opp = PmhalVmGetOppVoltage(vd, oppId);

    if (opp == NULL)
    {
        retVal = PM_BADARGS;
    }
    else
    {
        /*
         * See the ABB Programming Overview above.
         *
         * ABB Initialization:
         * -------------------
         * See PMHALVMInitABB() for details.
         *
         * NOTE: The initialization steps need to be performed
         *       only once at the system initialization; however,
         *       since we don't want to maintain state, we do
         *       the initialization every time.
         *
         * ABB Disable:
         * -----------
         *
         * To basic steps to leave ABB (entering bypass mode) are:
         * 1. Set the ACTIVE_FBB_SEL bit to 0U
         * 2. Set the OPP_SEL to 0U (to indicate bypass mode)
         * 3. Trigger the ABB LDO OPP change by setting OPP_CHANGE to 1
         * 4. Reset the VSET_OUT and FBB_MUX to 0U.
         *
         * Additionally the following needs to be ensured:
         * 1. Clear the ABB LDO transition completion interrupt
         *    before starting the enable sequence.
         * 2. Ensure OPP_CHANGE is zero (override if not) before setting the
         *    OPP_SEL.
         * 3. After triggering the OPP Change (step 5 above) wait for the
         *    transition to complete by checking the transition interrupt.
         */
        uint32_t irqStatus = 0U;

        /*
         * Clear retVal of PRCM interrupt for ABB LDO transition completion.
         */
        HW_WR_REG32(opp->prmABBDoneIRQStatRegAddr, opp->prmABBDoneStatMask);

        /*
         * Set ABB LDO FBB mode.
         */
        HW_WR_FIELD32(opp->prmABBLDOSetupRegAddr,
                      PRM_ABBLDO_DSPEVE_SETUP_ACTIVE_FBB_SEL,
                      PRM_ABBLDO_DSPEVE_SETUP_ACTIVE_FBB_SEL_BYPASS);

        /*
         * Ensure OPP_CHANGE is set to 0U and set OPP_SEL to Fast OPP.
         */
        HW_WR_FIELD32(opp->prmABBLDOCtrlRegAddr,
                      PRM_ABBLDO_DSPEVE_CTRL_OPP_CHANGE,
                      0x0U);
        HW_WR_FIELD32(opp->prmABBLDOCtrlRegAddr, PRM_ABBLDO_DSPEVE_CTRL_OPP_SEL,
                      PRM_ABBLDO_DSPEVE_CTRL_OPP_SEL_DEFAULT_NOMINAL);

        /*
         * Start the ABB LDO OPP Change.
         */
        HW_WR_FIELD32(opp->prmABBLDOCtrlRegAddr,
                      PRM_ABBLDO_DSPEVE_CTRL_OPP_CHANGE, 0x1U);

        /*
         * Wait till the transition is complete by checking the DONE bit.
         * The transition takes 50us; use 100us timeout delay to gives some
         * buffer.
         */
        timeout     = 100U;
        intOccurred = 0U;
        while ((intOccurred == 0U) && (timeout != 0U))
        {
            PMUtilsMinDelayUS((uint32_t) 1U);
            intOccurred = HW_RD_REG32(opp->prmABBDoneIRQStatRegAddr) &
                          opp->prmABBDoneStatMask;
            timeout = timeout - 1U;
        }

        if (timeout == 0U)
        {
            retVal = PM_TIMEOUT;
        }

        /*
         * Clear interrupt retVal.
         */
        irqStatus  = HW_RD_REG32(opp->prmABBDoneIRQStatRegAddr);
        irqStatus |= opp->prmABBDoneStatMask;
        HW_WR_REG32(opp->prmABBDoneIRQStatRegAddr, irqStatus);

        /*
         * Set the LDOVBBxxxVSET_OUT field and the MUX to zero.
         */
        HW_WR_FIELD32(opp->ctrlLDOVBBVoltageCtrlRegAddr,
                      PMHAL_VM_LDOVBB_VOLTAGE_CTRL_FBB_VSET_OUT,
                      0x0U);

        HW_WR_FIELD32(
            opp->ctrlLDOVBBVoltageCtrlRegAddr,
            PMHAL_VM_LDOVBB_VOLTAGE_CTRL_FBB_MUX_CTRL,
            PMHAL_VM_LDOVBB_VOLTAGE_CTRL_FBB_MUX_CTRL_EFUSE);
    }
    return retVal;
}

uint32_t PMHALVMSetSramLdoRetState(pmhalPrcmVdId_t            voltDomId,
                                   pmhalPrcmSramLdoRetState_t retState)
{
    pmErrCode_t retVal = PM_SUCCESS;
    const pmhalVmVoltageDomain_t *vd = NULL;
    vd = PmhalVmGetVoltageDomain(voltDomId);

    if (NULL == vd)
    {
        retVal = PM_BADARGS;
    }
    else
    {
        uint32_t compareVal = (uint32_t) ((uint32_t) 1U << (uint32_t) retState);
        if ((uint32_t) 0U != (compareVal & vd->sLdoValidRetMode))
        {
            uint32_t addr = vd->sldoCtrlAddr;
            if (PMHAL_REG_NOTAPPLICABLE != addr)
            {
                uint32_t fieldMask = ((uint32_t) 1U <<
                                      PMHAL_VM_SLDO_CTRL_RETMODE_ENABLE_SHIFT);
                uint32_t fieldShift = PMHAL_VM_SLDO_CTRL_RETMODE_ENABLE_SHIFT;

                HW_WR_FIELD32_RAW((uint32_t) addr,
                                  (uint32_t) fieldMask,
                                  (uint32_t) fieldShift, (uint32_t) retState);
            }
            else
            {
                retVal = PM_BADARGS;
            }
        }
        else
        {
            retVal = PM_BADARGS;
        }
    }

    return retVal;
}

uint32_t PMHALVMGetSramLdoTransState(pmhalPrcmVdId_t               voltDomId,
                                     pmhalPrcmSramLdoTransState_t *transState)
{
    pmErrCode_t retVal = PM_SUCCESS;
    const pmhalVmVoltageDomain_t *vd = NULL;
    vd = PmhalVmGetVoltageDomain(voltDomId);

    if ((NULL == vd) || (NULL == transState))
    {
        retVal = PM_BADARGS;
    }
    else
    {
        uint32_t addr = vd->sldoCtrlAddr;
        if (PMHAL_REG_NOTAPPLICABLE != addr)
        {
            uint32_t fieldMask = ((uint32_t) 1U <<
                                  PMHAL_VM_SLDO_CTRL_SRAM_IN_TRANSITION_SHIFT);
            uint32_t fieldShift = PMHAL_VM_SLDO_CTRL_SRAM_IN_TRANSITION_SHIFT;

            *transState = (pmhalPrcmSramLdoTransState_t)
                          HW_RD_FIELD32_RAW((uint32_t) addr,
                                            (uint32_t) fieldMask,
                                            (uint32_t) fieldShift);
        }
        else
        {
            retVal = PM_BADARGS;
        }
    }
    return retVal;
}

uint32_t PMHALVMGetSramLdoStatus(pmhalPrcmVdId_t           voltDomId,
                                 pmhalPrcmSramLdoStatus_t *ldoStatus)
{
    pmErrCode_t retVal = PM_SUCCESS;
    const pmhalVmVoltageDomain_t *vd = NULL;
    vd = PmhalVmGetVoltageDomain(voltDomId);

    if ((NULL == vd) || (NULL == ldoStatus))
    {
        retVal = PM_BADARGS;
    }
    else
    {
        uint32_t addr = vd->sldoCtrlAddr;
        if (PMHAL_REG_NOTAPPLICABLE != addr)
        {
            uint32_t fieldMask = ((uint32_t) 1U <<
                                  PMHAL_VM_SLDO_CTRL_SRAMLDO_STATUS_SHIFT);
            uint32_t fieldShift = PMHAL_VM_SLDO_CTRL_SRAMLDO_STATUS_SHIFT;

            *ldoStatus = (pmhalPrcmSramLdoStatus_t)
                         HW_RD_FIELD32_RAW((uint32_t) addr,
                                           (uint32_t) fieldMask,
                                           (uint32_t) fieldShift);
        }
        else
        {
            retVal = PM_BADARGS;
        }
    }
    return retVal;
}

uint32_t PMHALVMSetSramLdoSetup(pmhalPrcmVdId_t voltDomId,
                                uint32_t        setupVal)
{
    pmErrCode_t retVal = PM_SUCCESS;
    const pmhalVmVoltageDomain_t *vd = NULL;
    vd = PmhalVmGetVoltageDomain(voltDomId);

    if (NULL == vd)
    {
        retVal = PM_BADARGS;
    }
    else
    {
        uint32_t addr = vd->sldoSetupAddr;
        if (PMHAL_REG_NOTAPPLICABLE != addr)
        {
            /* To find the mask for the valid bits in the register*/
            uint32_t maskForSetup =
                (uint32_t) ((uint32_t) 1U <<
                            PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_COUNT) - 1U;
            uint32_t valToWrite = setupVal & maskForSetup;

            HW_WR_REG32(addr, valToWrite);
        }
        else
        {
            retVal = PM_BADARGS;
        }
    }
    return retVal;
}

uint32_t PMHALVMGetSramLdoSetup(pmhalPrcmVdId_t voltDomId,
                                uint32_t       *setupVal)
{
    pmErrCode_t retVal = PM_SUCCESS;
    const pmhalVmVoltageDomain_t *vd = NULL;
    vd = PmhalVmGetVoltageDomain(voltDomId);

    if ((NULL == vd) || (NULL == setupVal))
    {
        retVal = PM_BADARGS;
    }
    else
    {
        uint32_t addr = vd->sldoSetupAddr;
        if (PMHAL_REG_NOTAPPLICABLE != addr)
        {
            /* To find the mask for the valid bits in the register*/
            uint32_t maskForSetup =
                (uint32_t) ((uint32_t) 1U <<
                            PMHAL_PRCM_SLDO_SETUP_BIT_SHIFT_COUNT) - 1U;
            uint32_t valToRead = HW_RD_REG32(addr);
            *setupVal = valToRead & maskForSetup;
        }
        else
        {
            retVal = PM_BADARGS;
        }
    }
    return retVal;
}

pmErrCode_t PMHALVMGetDepCpuId(pmhalPrcmCpuId_t  cpuId,
                               pmhalPrcmCpuId_t *depCpuId)
{
    pmErrCode_t retVal = PM_SUCCESS;
    if (PMHAL_PRCM_CPU_ID_UNDEF < cpuId)
    {
        *depCpuId = pmhalDepCpuList[cpuId];
    }
    else
    {
        *depCpuId = PMHAL_PRCM_CPU_ID_UNDEF;
        retVal    = PM_BADARGS;
    }
    return retVal;
}

pmErrCode_t PMHALVMGetVoltageForOpp(pmhalPrcmVdId_t voltDomId,
                                    pmhalVmOppId_t  oppId,
                                    uint32_t       *voltage)
{
    pmErrCode_t status = PM_SUCCESS;
    const pmhalVmVoltageDomain_t *vd  = NULL;
    const pmhalVmOppVoltage_t    *opp = NULL;
    uint32_t    nomVoltageIndex       = 0U;
    uint32_t    readVoltage;

    /*
     * Check if the voltage domain id is valid and the OPP ID is valid
     * for this voltage domain.
     * PmhalVmGetVoltageDomain will return null if voltDomId is out of range.
     * PmhalVmGetOppVoltage will return null if vd is null or oppId
     * is out of range.
     */
    vd = PmhalVmGetVoltageDomain(voltDomId);

    opp = PmhalVmGetOppVoltage(vd, oppId);

    if (opp == NULL)
    {
        if (NULL == vd)
        {
            status = PM_INPUT_PARAM_BAD_VOLTAGE_ID;
        }
        else
        {
            status = PM_BADARGS;
        }
    }
    else
    {
        pmhalPrcmPmicRegulatorId_t regId =
            PmhalVmGetRegulatorId(voltDomId);
        nomVoltageIndex = PmhalVmGetVoltageIndex();
        readVoltage     = 0U;
        if (opp->isAVSSupported == TRUE)
        {
            readVoltage = PMHALVMGetAVS0EfuseVoltage(voltDomId,
                                                     (pmhalVmOppId_t) oppId);
        }
        else
        {
            readVoltage = opp->nomVoltage[nomVoltageIndex];
        }
        *voltage = PMHALPmicGetConvRegulatorVoltage(regId, readVoltage);
    }
    return status;
}

pmErrCode_t PMHALVMGetCpuInVoltageDomain(pmhalPrcmVdId_t    voltDomId,
                                         pmhalPrcmCpuId_t **cpuIdArray,
                                         uint32_t          *numCpus)
{
    pmErrCode_t status = PM_SUCCESS;
    const pmhalVmVoltageDomain_t *vd = NULL;
    vd = PmhalVmGetVoltageDomain(voltDomId);
    if (NULL == vd)
    {
        status = PM_BADARGS;
    }
    else
    {
        *cpuIdArray = vd->cpuIdArr;
        *numCpus    = vd->numCpus;
    }
    return status;
}

/* -------------------------------------------------------------------------- */
/*                 Internal Function Definitions                              */
/* -------------------------------------------------------------------------- */

static uint32_t PmhalVmGetWtCnt(void)
{
    /*
     * The formula is as follows:
     * wtcnt = LDO settling time / (number of sys_clk cycles / SYS_CLK_RATE)
     *
     * where LDO settling time for TRA2xx is 50 uSec,
     * number of sys_clk cycles is 16  AND
     * the SYS_CLK rate is as configured by the application and can be one
     * of the following values in MHz: 12, 13, 19.2, 20, 26, 38.4
     *
     * NOTE: At present this function hard codes the sys_clk frequency
     * of 20MHz as the SBL sets this sys_clk frequency. This needs to be
     * updated to query the PRCM HAL once this API is implemented in
     * PRCM HAL.
     *
     * WTCNT values table
     *
     *      SYS_CLK (MHz)            WTCNT Value
     *      ------------------------------------
     *          12                     0x26
     *          13                     0x29
     *          19.2                   0x3C
     *          20                     0x3D
     *          26                     0x52
     *          38.4                   0x78
     */

    uint32_t wtCntVal;
    uint32_t sysClk;

    sysClk = PMHALCMGetSysClockFreq();

    wtCntVal = (((uint32_t) sysClk *
                 PMHAL_VM_ABB_SR2_WTCNT_TIME) /
                (16U * 1000U));

    return wtCntVal;
}

static uint32_t PmhalVmGetVoltageIndex(void)
{
    uint32_t nomVoltageIndex = 0U;
    uint32_t packageType     =
        HW_RD_FIELD32(PMHAL_VM_PACKAGE_READ_ADDR, PMHAL_VM_PACKAGE_BIT);
    if (PMHAL_VM_PACKAGE_TYPE_0 == packageType)
    {
        nomVoltageIndex = 1U;
    }
    else
    {
        nomVoltageIndex = 0U;
    }
    return nomVoltageIndex;
}

Q3/A3 : Can you compare these registers

So base on Q2/A2, I assume SBL detect "ABB Support  or not" which is depend on "ABBEN" bit.

Related register for TDA2EG_17.

Al of them "ABBEN" bit is false.

Curious to know : 

(1) Which register define "oppVoltage->isABBSupported" or not?

pmErrCode_t PMHALVMSetOpp(pmhalPrcmVdId_t voltDomId, pmhalVmOppId_t oppId,
                          uint32_t timeout)
{
    pmErrCode_t retVal = PM_SUCCESS;
    const pmhalVmVoltageDomain_t    *vd         = NULL;
    const pmhalVmOppVoltage_t       *oppVoltage = NULL;
    uint32_t    volt_mv         = 0U;
    uint32_t    isABBEnable     = 0U;
    uint32_t    curr_mv         = 0U;

    /*
     * Check if the voltage domain id is valid and the OPP ID is valid
     * for this voltage domain.
     * PmhalVmGetVoltageDomain will return null if voltDomId is out of range.
     * PmhalVmGetOppVoltage will return null if vd is null or oppId
     * is out of range.
     */
    vd = PmhalVmGetVoltageDomain(voltDomId);
    if (NULL == vd)
    {
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PmhalVmGetVoltageDomain() return null\n");
        retVal = PM_INPUT_PARAM_BAD_VOLTAGE_ID;
    }
    else
    {
        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] pmhalVmGetOppVoltage() start\n");
        oppVoltage = PmhalVmGetOppVoltage(vd, oppId);
        if (oppVoltage == NULL)
        {
            SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] return failed\n");
            retVal = PM_BADARGS;
        }
    }

    if (PM_SUCCESS == retVal)
    {
        /*
         * Get the AVS Class-0U voltage to be used.
         */
        volt_mv = PMHALVMGetAVS0EfuseVoltage(voltDomId, oppId);

        if (volt_mv != 0U)
        {

            SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PMHALVMGetAVS0EfuseVoltage() ok \n");

            /*
            * Get the current value of the voltage rail.
            * This will be used to compare against the desired voltage.
            * If the rail is already configured for this exact voltage setting
            * there is no need to again set the voltage.
            */
            retVal = PMHALVMGetCurrentVoltage(voltDomId, &curr_mv);

            /*
             * Nothing to be done if the current voltage rail is the same
             * as the desired voltage.
             */
            if ((retVal == PM_SUCCESS) && (curr_mv != volt_mv))
            {
                SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PPMHALVMGetCurrentVoltage() ok \n");

                /*
                 * ABB Programming Overview:
                 * -------------------------
                 *
                 * ABB LDO supports two modes, namely bypass mode and
                 * FBB mode. The mode name FBB is used for historical
                 * reason but enabling the FBB mode can result in
                 * Forward Body Bias (FBB) or Reverse Body Bias (RBB)
                 * depending on the VSET_OUT value programmed.
                 *
                 * When changing OPP, if the old OPP required ABB then,
                 * we need to disable (put ABB LDO in bypass mode),
                 * change the voltage and if the new OPP requires ABB,
                 * enable ABB.
                 *
                 * The ABB first needs to be initialized.
                 * See PMHALVMInitABB() for details.
                 *
                 * NOTE: The initialization steps need to be performed
                 *       only once at the system initialization;
                 *       however, since we don't want to maintain
                 *       state, we do the initialization every time.
                 *
                 * The Setup and Control registers to program ABB
                 * are described in PMHALVMEnableABB().
                 *
                 * NOTE: The oppVoltage structure represents the
                 *       new OPP we need to enter into; however, we need
                 *       to check if the current OPPrequired ABB. Since
                 *       the same control/retVal registers are used for
                 *       a given VD, we can use the new OPP structure
                 *       to check if the current OPP required ABB.
                 */

                pmhalPrcmPmicRegulatorId_t regId = PmhalVmGetRegulatorId(
                    voltDomId);

                if (oppVoltage->isABBSupported == TRUE)
                {
                    uint32_t vminAbbEn;

                    SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] isABBSupported == TRUE \n");

                    PMHALVMInitABB(voltDomId, oppId);
                    isABBEnable = (uint32_t) PMHALVMIsABBEnabled(voltDomId,
                                                                 oppId);
                    if (isABBEnable == TRUE)
                    {
                        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PMHALVMDisableABB() \n");
                        retVal = PMHALVMDisableABB(voltDomId, oppId);
                    }

                    if (PM_SUCCESS == retVal)
                    {
                        SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PMHALPmicSetRegulatorVoltage() \n");
                        retVal = PMHALPmicSetRegulatorVoltage(regId, volt_mv,
                                                              timeout,
                                                              (uint32_t) TRUE);
                    }
                    if (PM_SUCCESS == retVal)
                    {
                        vminAbbEn =
                            HW_RD_FIELD32(oppVoltage->fuseOPPVminRegAddr,
                                          PMHAL_VM_STD_FUSE_OPP_VMIN_ABBEN);

                        if (vminAbbEn != 0U)
                        {
                            SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PPMHALVMEnableABB() \n");
                            retVal = PMHALVMEnableABB(voltDomId, oppId);
                        }
                    }
                }
                else
                {
                    SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] isABBSupported == false \n");
                    SBLLibPrintf(SBLLIB_TRACE_LEVEL_IMP_INFO, "\n[Gibbs][pmhal_vm.c] PMHALPmicSetRegulatorVoltage() \n");
                    retVal = PMHALPmicSetRegulatorVoltage(regId, volt_mv,
                                                          timeout,
                                                          (uint32_t) TRUE);
                }
            }
        }

(2) Is TDA2EG-17 support ABB? I am a little bit confuse.

Thank You.

Gibbs

Thank you Jouse,

Let's use this patch for testing, and keep monitor does it have any side effect or not.

Gibbs

Sounds good, please keep me updated. 

Note:  If this answer solves your question please mark post as "Answered"

Hi Josue,

Hi Kevin,

I was trying to disable this ABB setup without commenting out the whole function as in Gibbs patch. It seems like I failed to do so. 

Gibbs patch should also work fine as well. 

If his patch works for you then you can keep that one. This feature is not a necessary one and I believe it should not affect your functionality much.

Please see my previous comments:

Josue Zamitiz-Ayala said:

Anyhow, I've heard back from the HW team and ABB can be disabled. 

Have you seen any side effects?

-Josue

It’s working properly at the moment.

thank you,

Kevin Hsu

Hi Kevin,

I see why the first patch I shared failed, SBL is calling PMHALVMEnableABB() directly.

File sbl_utils_tda2xx.c at line 2493. My first fix was assuming  isABBSupported check would be enough. I think the fact that Gibbs's patch works confirms that this function is being called still as I have found.

If you would like to try another patch, try this one: disable_abb_tda2ex_v2, ignore the first patch.

The only difference from Gibbs' patch is that this one will return PM_SUCCESS instead of returning PM_TIMEOUT, reducing any issues down the road. I think the only issue might just be an error code.. 

Do you see any error prints with the current working patch? 

-Josue

Hi Josue,

Your V2 Patch i can not download

but i modify the code with your recommand , it successfully to eliminate the error massage

Thank you a lot ~

Kevin Hsu

Good to hear this worked out!

Sorry about the patch!

Here's another try: https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/disable_5F00_abb_5F00_tda2ex_5F00_v2.patch

-Josue