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DRA829J-Q1: CTRLMMR_PADCONFIG register - pin assignment

Peter Fritzenschaft
Intellectual 441 points

Part Number: DRA829J-Q1

Hello,

Table 5-125 of SPRSP35K gives the link between Ball Number and PADCONFIG Register.

Following Registers are not listed in this table but in SPRUIL1 Table 6-2:

CTRLMMR_PADCONFIG18, CTRLMMR_PADCONFIG171, CTRLMMR_PADCONFIG172

Are these registers applicable for any pin of DRA829J-Q1?

Further, register CTRLMMR_PADCONFIG171 is mentioned in notes below SPRSP35K Table 5-88 with reference to Signal MMC1_CLK (ball P25), but this ball is assigned to PADCONFIG148 in Table 5-125.

Same for CTRLMMR_PADCONFIG171 below Table 5-88.

Regards, Peter

  • +1
    TI__Guru 57427 points

    Hi Peter,

    All three of those PADCONFIG registers are for signals that exist on the die but are not pinned out to a package BGA.

    The PADCONFIG171 and PADCONFIG172 are for a "loopback clock" that is internally connected to the MMC1_CLK and MMC2_CLK.  That's why the RX path needs to be enabled.

    PADCONFIG18 has no function.

    Regards,

    Kyle

  • +1
    TI__Expert 7710 points

    Hi Peter,

    PADCONFIG18 is responsible for the loopback clock of the GPMC interface. Its RX will need to be enabled for synchronous operations (ie. capturing data).