Part Number: AM625
Hi Hong,
Could you review the flow, address and concept, the one we follow the application, to confirm whether it could be possible to do on hard code or not?
I follow the application note :
Added this api in the spl_atf.c bf atf_entry();
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“
#include <asm/io.h>
/* WKUP CTRL MMR unlock */
#define WKUP_CTRL_MMR_LOCK0_KICK0 0x43001008
#define WKUP_CTRL_MMR_LOCK0_KICK1 0x4300100C
/* MAIN CTRL MMR unlock (clock select) */
#define MAIN_CTRL_MMR_LOCK2_KICK0 0x43009008
#define MAIN_CTRL_MMR_LOCK2_KICK1 0x4300900C
#define MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL 0x43008380
/* WKUP RTI0 base = 0x2B000000 */
#define WKUP_RTI0_BASE 0x2B000000
#define RTI_WWDCTRL (WKUP_RTI0_BASE + 0x090)
#define RTI_WWDPRLD (WKUP_RTI0_BASE + 0x094)
#define RTI_WWDRXNCTRL (WKUP_RTI0_BASE + 0x0A4)
/* Enable and Disable values */
#define RTI_DWD_ENABLE 0xA98559DA
#define RTI_DWD_DISABLE 0x5312ACED
static void wkup_rti0_enable_reset_watchdog(void)
{
/* Unlock WKUP CTRL MMR */
mmio_write_32(WKUP_CTRL_MMR_LOCK0_KICK0, 0x68EF3490);
mmio_write_32(WKUP_CTRL_MMR_LOCK0_KICK1, 0xD172BC5A);
/* Unlock MAIN CTRL MMR */
mmio_write_32(MAIN_CTRL_MMR_LOCK2_KICK0, 0x68EF3490);
mmio_write_32(MAIN_CTRL_MMR_LOCK2_KICK1, 0xD172BC5A);
/* Select RTI clock (example: 32kHz) */
mmio_write_32(MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL, 0x3);
/* Reaction = SoC Reset */
mmio_write_32(RTI_WWDRXNCTRL, 0x5);
/* Set preload (timeout window) */
mmio_write_32(RTI_WWDPRLD, 0x23);
/* Enable watchdog counter */
mmio_write_32(RTI_WWDCTRL, RTI_DWD_ENABLE);
}
“
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Add disable api in the board_r.c / board_late_init()
“
#define WKUP_RTI0_BASE 0x2B000000
#define RTI_DWD_DISABLE 0x5312ACED
#define RTI_WWDCTRL (WKUP_RTI0_BASE + 0x090)
“
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Uboot close wdt command
“
mmio_write_32(RTI_WWDCTRL, RTI_DWD_DISABLE);
“
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