[FAQ] AM6421: RESETSTATz output during ROM boot

Joe Paolino

Part Number: AM6421

Hello,

During a successful QSPI boot, I have captured the following signals: MCU_PORz, RESETSTATz, OSPI_CLK, OSPI_CS. I'm observing that roughly 35mS after RESETSTATz goe high it has a 160uS period where it drops low. Looking at the logic capture and identical timing characteristics it appears that ROM boot occurs twice. Is this expected behavior?

4 months ago

0 Kallikuppa Sreenivasa 4 months ago

TI__Guru**** 219400 points

Hello Joe Paulino,

Thank you for the query.

Can you please probe the Reser_REQz, MCU_RESETz input along with PORz_OUT, RESETSTATz and MCU_RESETSTATz signals.

Can you share the schematics that shows the processor input and output connection including the source in a searchable PDF.

Regards,

Sreenivasa

0 Joe Paolino 3 months ago in reply to Kallikuppa Sreenivasa

Intellectual 580 points

Hello Sreenivasa,

I have captured the signals as you requested MCU_RESETSTATz drops low at the same moment as resetstatz, but the others remain unchanged. I have also provided a couple of pages of the schematic that include power and reset to the processor.

minsch.pdf

Thank you,

Joe

0 Kallikuppa Sreenivasa 3 months ago in reply to Joe Paolino

TI__Guru**** 219400 points

Hello Joe Paulino,

Thank you for the inputs.

Let me review the inputs and come back.

Do you have provision for an alternate boot ? If yes can you please confirm the behavior.

Regards,

0 Dominic Rath 3 months ago in reply to Kallikuppa Sreenivasa

Mastermind 7730 points

Hi,

could you explain *what* you're booting? If this is e.g. U-Boot or a SBL with provisions for the i2368/i2331 errata, the bootloader will warm-reset the processor after the first boot, causing the ROM to load the bootloader image a second time. This also matches PORz_OUT remaining high, while RESETSTATz and MCU_RESETSTATz briefly go low.

Regards,

Dominic

0 Joe Paolino 3 months ago in reply to Dominic Rath

Intellectual 580 points

Hi Dominic, our configuration of the AM64 uses FreeRTOS on two R5 cores only. Our bootloader and application images load from OSPI successfully.

We do not use the A53, M4, PRU-ICSSG (i2368), or CPSW (i2331). Is the BOOT ROM hard coded to issue a warm reset regardless of the boot media and processors/peripherals in use? Please elaborate.

Thank you,

Joe

+1 Dominic Rath 3 months ago in reply to Joe Paolino

Mastermind 7730 points

Hello Joe,

this warm reset is implemented in the SBL, not in the ROM. You could check your own bootloader for this code sequence:

https://github.com/TexasInstruments/mcupsdk-core/blob/6a622a5c2729c5ad10ba066646944609dc0c64bb/examples/drivers/boot/sbl_ospi/am64x-evm/r5fss0-0_nortos/main.c#L71

The implementation for Bootloader_socResetWorkaround is here:

https://github.com/TexasInstruments/mcupsdk-core/blob/6a622a5c2729c5ad10ba066646944609dc0c64bb/source/drivers/bootloader/soc/am64x_am243x/bootloader_soc.c#L1249

If your application doesn't (and wont ever) use PRU-ICSSG or CPSW, I guess you could disable this code.

What happens is the boot ROM loads your code, the code detects the reset reason was a cold boot or a PORz, and executes a warm reset. Boot ROM loads your code for the second time, the reset reason is a warm boot, and your bootloader continues.

Regards,

Dominic

0 Joe Paolino 3 months ago in reply to Dominic Rath

Intellectual 580 points

Dominic, thanks for this clear explanation and path forward.

0 Kallikuppa Sreenivasa 3 months ago in reply to Joe Paolino

TI__Guru**** 219400 points

Hello Dominic,

Thank you for the inputs, appreciated.

Regards,

Sreenivasa

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[FAQ] AM6421: RESETSTATz output during ROM boot