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C6670 PLL Settings and Debugger

Erick Higa
Intellectual 860 points
Other Parts Discussed in Thread: TMS320C6670

I'm having a problem connecting to the C6670 with a XDS560v2 on a custom board after setting the PLL to set the core frequency to 1.2GHz.  I'm using a 100 MHz input clock, and are bringing the device up in "No Boot" Mode. I'm using the latest Code Composer Studio (Version: 5.1.0.201109191500  Build id: N201109191500).

If I don't load a GEL file when connecting, the PLL is not set, (scoping SYSCLKOUT reads ~16MHz ~= 100MHz/6)

So I've used the evm6670l.gel file and have modifed the following settings:

#define PLL1_M 47
#define PLL1_D 1
#define REF_CLOCK_KHZ 100000

When the GEL file runs upon connecting, it looks like it loads fine and says it's running @1200MHz  (scoping SYSCLKOUT reads ~200MHz ~= 1200MHz/6).  The problem is that once this is set, I get various errors on the XDS560v2, not being able to verify code loads, or the debugger disconnecting until I do a "system reset", then I can connect and load code again, but then the processor is back to running at 100MHz.

I've also tried setting the PLL in code, and it seems to react the same way, where I can step through the debugger, but once the PLL is set to run at 1.2GHz, the debugger looses connection, cannot halt, or some other error. (I do also verify the SYSCLKOUT are the correct values)

When I set the PLL to run at 600/800MHz, it does not seem to have this issue while also 1GHz has this issue.

Any help would be greatly appreciated, thanks,

Erick

  • 0
    TI__Guru* 84110 points

    Erick,

    My thoughts are:

    1. Try lower speeds first to see if your settings will work at the lower speeds.

    2. Compare your PLL1 frequency with the specs for the maximum and minimum clock rates for the PLL.

    3. Consider using different numbers for _M and _D that will get the same output value with a different internal frequency (maybe higher, maybe lower, depending on the spec limits).

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 860 points

    Hey Randy,

    Sorry, I don't think my last paragraph statement was clear.  I did change the M/D settings for it to work at 600/800 MHz, and it has no problem running and it does not lose connection w/ the debugger (I verified with a scope that SYSCLKOUT was at 100/133 MHz respectively).  I did however try 1000MHz and the behavior was the same as when trying to run at 1200MHz. 

    It is my understanding from the Datasheet (sprs689c) that it should be able to run at 1000/1200 MHz.

    Erick

  • 0 in reply to Erick Higa
    Intellectual 860 points

    Ok, here's more info to see if someone can help me figure this out, I've set the GPIO PORT to 0x 1B83, which means the boot pins BOOTMODE[12..0] are at 0x0DC1 (110111000001b).  This is the proper setup for a 100MHz input to boot up in SRIO boot mode (5Gbps using a 312.5MHz ref clock) running at 1.2GHz. Again, the SYSCLKOUT was verified at 200MHz, and when the debugger connects, it gets to the point where it starts to load the code and I get the JTAG errors again

    C66xx_0: File Loader: Data verification failed at address 0x00817FF0 Please verify target memory and memory map.
    C66xx_0: GEL: File: xxxxxxxxxxxxxx\proj.out: a data verification error occurred. file load failed.

    Now when I try to reconnect to the device it cannot connect again w/o power cycling the device and relaunching the debugger.  If I set the boot PLL to 800 MHz or lower it seems to run fine again and connect with the debugger. Can someone verify for me that the TMS320C6670 can operate at 1.2GHz, and that there are no "slow" versions of it that are not capable of that?

    There are other things I can work on that 800MHz will be fine for as far as development, however we are migrating to this from a 6474 for the supposed improved speeds, if 1.2GHz is not possible to debug in, we need to know ASAP.

  • 0 in reply to Erick Higa
    TI__Guru* 84110 points

    Erick,

    The device datasheet is the place to look for the operating speed and speed grades available for the C6670. There is a table with the "device nomenclature" that will help you figure out if the devices on your board are rated at full speed.

    Yes, if the device is rated to operate at 1.2GHz then it will also be debuggable at that speed.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 860 points

    Hmmm, After looking at the part I guess it's supposed to be a 1000MHz part, although I do have a question about that, in section 2.5.3 (PLL Settings) of the bootmode using Table 2-13 C66x CorePac System PLL Configuration, it says that setting the bootmode pins should give it the correct PLL M/D settings depending on the part. (i.e. 0b011 for the bootmode using a 100 MHz clock will set the D to 0 and M to 19 to give us a 1000MHz sysclk when booted since it is a 1000MHz part).  On our part it is clearly setting it to 0 and 23 respectively, trying to boot it at 1200MHz using our 100MHz input.  Am I misinterpreting the datasheet or is it an error in my particular part?

  • 0 in reply to Erick Higa
    TI__Guru* 84110 points

    Erick,

    What do you see on the device markings? All of them could be helpful, please.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 860 points

    Thanks Randy,

    Here are all the markings:

    TMX320C6670CYP
    YB10A-15AQLEC
    ©2010 TI 2 G1

    Erick