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AM2754-Q1: AM2754 .cio section

IChung
Intellectual 480 points

Part Number: AM2754-Q1

Hi,

I am using the C7x core of the AM2754. When the .cio section is placed in L2SRAM, there is no issue, but when it is placed in MSRAM, the following problem occurs:

Invalid CIO command (2) in the CIO buffer at address (0x80200000) was not recognized. Please disable interrupts while running.

Both L2RAM and MSRAM are configured as Outer Shareable, Normal outer and inner write-back cacheable non-transient memory.
Is the .cio section required to be placed only in L2SRAM?

  • 0
    TI__Genius 14620 points

    Hi,

    Can you share which version of CCS are you using and your linker script?

    Thanks,
    Shreyansh

  • 0 in reply to Shreyansh Anand
    Intellectual 480 points

    The CCS version I am using is 12.8.1. Below is the linker.cmd file.


    --ram_model
    -heap 0x4000
    -stack 0x4000
    --args 0x1000
    --cinit_compression=off
    -e _c_int00_secure

    /******************************************************************************/
    /* The SRAM address is aliased as follows for C7x for enabling CacheWT */
    /* SRAM Address | Aliased address | Size */
    /* 0x72000000 | 0x80000000 | 0x600000 */
    /******************************************************************************/

    MEMORY
    {
    C75_0_L2SRAM_ENTRY (RWIX) : ORIGIN = 0x7E000000 LENGTH = 0x00000100
    C75_0_L2SRAM (RWX) : ORIGIN = 0x7E000100 LENGTH = 0x00200000 - 0x100
    C75_0_L2SRAMAUX (RWX) : ORIGIN = 0x7E200000 LENGTH = 0x00040000

    C75_0_OCRAM_STATIC (RWIX) : ORIGIN = 0x80000000 LENGTH = 0x00200000
    C75_0_OCRAM_DATA_CN (RWIX) : ORIGIN = 0x80200000 LENGTH = 0x00200000
    C75_0_OCRAM_EXT (RWIX) : ORIGIN = 0x80400000 LENGTH = 0x00200000

    //C75_HYPERRAM (RW) : ORIGIN = 0x68000000 LENGTH = 0x04000000 // 64MB HyperRAM
    }

    SECTIONS
    {
    .sram_start START(_sram_start) > C75_0_L2SRAM NOINIT
    .vecs > C75_0_L2SRAMAUX ALIGN(0x200000)

    .l1dmemory > C75_0_L2SRAM
    .l2dmemory > C75_0_L2SRAM
    .text > C75_0_L2SRAM
    .text:touch > C75_0_L2SRAM
    .text:_c_int00_secure > C75_0_L2SRAM_ENTRY

    .neardata: > C75_0_L2SRAM
    .rodata: > C75_0_L2SRAM
    .bss: > C75_0_L2SRAM
    RUN_START(__BSS_START)
    RUN_END(__BSS_END)

    .init_array: > C75_0_L2SRAM
    .far: > C75_0_L2SRAM
    .fardata: > C75_0_L2SRAM
    .neardata > C75_0_L2SRAM
    .rodata > C75_0_L2SRAM
    .data: > C75_0_L2SRAM
    .switch: > C75_0_L2SRAM
    .stack: > C75_0_L2SRAM
    .args: > C75_0_L2SRAM align = 0x4, fill = 0 {_argsize = 0x200; }
    .sysmem: > C75_0_L2SRAM
    .cinit: > C75_0_OCRAM_EXT
    .const: > C75_0_L2SRAM START(const_start) SIZE(const_size)
    .pinit: > C75_0_L2SRAM
    .cio: > C75_0_L2SRAM
    .stack: > C75_0_L2SRAM
    .ddrData > C75_0_OCRAM_DATA_CN

    .staticData > C75_0_OCRAM_EXT
    .l2sramaux > C75_0_L2SRAMAUX
    .coeffMemory > C75_0_OCRAM_EXT
    xdc.meta: > C75_0_L2SRAM, type = COPY


    GROUP: > C75_0_L2SRAM
    {
    .data.Mmu_tableArray : type=NOINIT
    .data.Mmu_tableArraySlot : type=NOINIT
    .data.Mmu_level1Table : type=NOINIT
    .data.gMmu_tableArray_NS : type=NOINIT
    .data.Mmu_tableArraySlot_NS : type=NOINIT
    .data.Mmu_level1Table_NS : type=NOINIT
    }

    }