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Part Number: DRA821U
Other Parts Discussed in Thread: DRA821
Hi Team,
We are planning to implement the 10G interface on the DRA821U processor. Could you please guide us the implementation required to support and validate the 10G interface on DRA821U? Any reference documents, configuration steps, or validation guidelines would be very helpful for our implementation.
Looking forward to your guidance.
Thanks and Regards,
Subashini
Hi,
Could you please share more details about the application you are planning to use for CPSW5G from the DRA821?
I mean the ETHFW applicaiton or a native Linux driver.
The native Linux driver, please integrate the following patch.
From cb531ca97288111e7513f79d669d43f6a19987c5 Mon Sep 17 00:00:00 2001
From: Siddharth Vadapalli <s-vadapalli@ti.com>
Date: Sun, 4 Feb 2024 12:13:57 +0530
Subject: [PATCH 3/3] arm64: dts: ti: k3-j7200: Enable fixed-link USXGMII for
CPSW5G MAC Port 1
Configure Serdes0 and Serdes_Wiz0 for supporting USXGMII mode of
operation. USXGMII mode requires 156.25 MHz clock.
Additionally, configure the device-tree node for CPSW5G's MAC Port 1 to
operate in fixed-link USXGMII mode at 10Gbps.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
.../dts/ti/k3-j7200-common-proc-board.dts | 34 +++++++----
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 56 +++++++------------
2 files changed, 41 insertions(+), 49 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index b13ea4681a41..899679c28bfd 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -343,32 +343,42 @@ &serdes_refclk {
};
&serdes0 {
- serdes0_pcie_link: phy@0 {
- reg = <0>;
- cdns,num-lanes = <2>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_PCIE>;
- resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
- };
-
- serdes0_qsgmii_link: phy@1 {
+ serdes0_usxgmii_link: phy@1 {
reg = <2>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_QSGMII>;
+ cdns,phy-type = <PHY_TYPE_USXGMII>;
resets = <&serdes_wiz0 3>;
};
};
+&cpsw0 {
+ status = "okay";
+ pinctrl-names = "default";
+};
+
+&cpsw0_port1 {
+status = "okay";
+ phy-mode = "usxgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 1>, <&serdes0_usxgmii_link>;
+ phy-names = "mac", "serdes";
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
+};
+
&pcie1_rc {
reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
- phys = <&serdes0_pcie_link>;
+ //phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
+ status = "disabled";
};
&pcie1_ep {
- phys = <&serdes0_pcie_link>;
+ //phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 57106dfe16c8..78993b54a677 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -5,6 +5,7 @@
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/phy/phy-ti.h>
/ {
serdes_refclk: serdes-refclk {
#clock-cells = <0>;
@@ -662,56 +663,37 @@ main_sdhci1: mmc@4fb0000 {
};
serdes_wiz0: wiz@5060000 {
- compatible = "ti,j721e-wiz-10g";
+ compatible = "ti,j7200-wiz-10g";
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
- clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>, <&k3_clks 292 89>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
num-lanes = <4>;
#reset-cells = <1>;
- ranges = <0x5060000 0x0 0x5060000 0x10000>;
+ ranges;
+ #clock-cells = <1>;
+ ti,scm = <&scm_conf>;
assigned-clocks = <&k3_clks 292 85>;
- assigned-clock-parents = <&k3_clks 292 89>;
-
- wiz0_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 292 85>, <&serdes_refclk>;
- clock-output-names = "wiz0_pll0_refclk";
- #clock-cells = <0>;
- assigned-clocks = <&wiz0_pll0_refclk>;
- assigned-clock-parents = <&k3_clks 292 85>;
- };
-
- wiz0_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 292 85>, <&serdes_refclk>;
- clock-output-names = "wiz0_pll1_refclk";
- #clock-cells = <0>;
- assigned-clocks = <&wiz0_pll1_refclk>;
- assigned-clock-parents = <&k3_clks 292 85>;
- };
-
- wiz0_refclk_dig: refclk-dig {
- clocks = <&k3_clks 292 85>, <&serdes_refclk>;
- clock-output-names = "wiz0_refclk_dig";
- #clock-cells = <0>;
- assigned-clocks = <&wiz0_refclk_dig>;
- assigned-clock-parents = <&k3_clks 292 85>;
- };
-
- wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
- clocks = <&wiz0_refclk_dig>;
- #clock-cells = <0>;
- };
+ assigned-clock-parents = <&k3_clks 292 88>;
+ assigned-clock-rates = <156250000>;
serdes0: serdes@5060000 {
- compatible = "ti,j721e-serdes-10g";
+ compatible = "ti,j7200-serdes-10g";
reg = <0x05060000 0x00010000>;
reg-names = "torrent_phy";
resets = <&serdes_wiz0 0>;
reset-names = "torrent_reset";
- clocks = <&wiz0_pll0_refclk>;
- clock-names = "refclk";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>;
+ clock-names = "refclk", "refclk1";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 292 85>,
+ <&k3_clks 292 89>,
+ <&k3_clks 292 85>;
#address-cells = <1>;
#size-cells = <0>;
};
--
Hi Sudheer,
I am using the native Linux driver for 10G validation, and I have a question. I have applied the patch you provided, and currently I have the following pin configuration for the 10G interface.
Do I need to add these pins to my DTSI file? If they are required, could you please confirm which pins are mandatory and guide me on how to configure them in the DTSI file?
| Functionality | Pad name | Pin number | Gpio no | Input/Output |
| SGMII1_TX0_N | MCU_RGMII1_TD1/MCU_RMII1_TXD1/WKUP_GPIO0_46 | B11 | - | Output |
| SGMII1_TX0_P | MCU_RGMII1_TD0/MCU_RMII1_TXD0/WKUP_GPIO0_47 | D10 | - | Output |
| SGMII1_RX0_N | MCU_RGMII1_RD1/MCU_RMII1_RXD1/WKUP_GPIO0_52 | B9 | - | Input |
| SGMII1_RX0_P | MCU_RGMII1_RD0/MCU_RMII1_RXD0/WKUP_GPIO0_53 | A9 | - | Input |
| ETH_10G_MDC | MCU_MDIO0_MDC/WKUP_GPIO0_55 | D9 | - | Output |
| ETH_10G_MDIO | MCU_MDIO0_MDIO/WKUP_GPIO0_54 | C9 | - | Input/Output |
| ETH_10G_RSTn(GPIO_A_1) | EXT_REFCLK1/SYNC1_OUT/CPTS0_HW2TSPUSH/UART3_TXD/SPI7_CLK/I2C1_SDA/GPIO0_59 | T3 | GPIO0_59 | Output |
| ETH_10G_INTn(GPIO_A_0) | ECAP0_IN_APWM_OUT/SYNC0_OUT/CPTS0_RFT_CLK/CPTS0_HW1TSPUSH/UART3_RXD/SPI7_CS0/I2C1_SCL/GPIO0_58 | U3 | GPIO0_58 | Input |
| RSTOUT(GPIO_A_2) | I2C0_SCL/GPIO0_56 | V3 | GPIO0_56 | Output |
Thanks and Regards,
Subashini
Hi,
Do I need to add these pins to my DTSI file? If they are required, could you please confirm which pins are mandatory and guide me on how to configure them in the DTSI file?
Yes, you need to add all pins used for 10G PHY.
Additionally, if you are using MDIO pins (instead of fixed link) to communicate with the PHY, you need to use the Main CPSW5G MDIO pins, not the MCU MDIO pins.
SGMII1_TX0_N MCU_RGMII1_TD1/MCU_RMII1_TXD1/WKUP_GPIO0_46 B11 - Output SGMII1_TX0_P MCU_RGMII1_TD0/MCU_RMII1_TXD0/WKUP_GPIO0_47 D10 - Output SGMII1_RX0_N MCU_RGMII1_RD1/MCU_RMII1_RXD1/WKUP_GPIO0_52 B9 - Input SGMII1_RX0_P MCU_RGMII1_RD0/MCU_RMII1_RXD0/WKUP_GPIO0_53
SerDes lanes are independent pins (As SERDES0_TXn_P, SERDES0_TXn_N, SERDES0_RXn_P, SERDES0_RXn_N, where n is 0 to 3 serdes lane number ), not multiplexed with any other pins.
Best Regards,
Sudheer
Hi Sudheer,
I have added the 10G-related pins in my DTSI file. I have a question regarding the PCIe configuration in our project.
We are using an x16 Endpoint PCIe. If I remove the serdes0_pcie_link node, will it affect the Endpoint PCIe functionality?
Do I need to remove this node to validate the 10G configuration?
For now, I have not removed the serdes0_pcie_link node from my DTSI files. I have attached the updated DTSI changes for your reference. If I have missed anything or if further changes are required, could you please point them out?diff -Naur --no-dereference A/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts B/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
--- A/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts 2025-11-03 10:14:31.636501044 +0530
+++ B/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts 2026-01-23 11:23:37.220907765 +0530
@@ -422,12 +422,12 @@
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
};
-
- serdes0_qsgmii_link: phy@1 {
+
+ serdes0_usxgmii_link: phy@1 {
reg = <2>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_QSGMII>;
+ cdns,phy-type = <PHY_TYPE_USXGMII>;
resets = <&serdes_wiz0 3>;
};
};
@@ -437,10 +437,11 @@
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
+ status = "disabled";
};
&pcie1_ep {
- phys = <&serdes0_pcie_link>;
+ //phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
status = "disabled";
diff -Naur --no-dereference A/arch/arm64/boot/dts/ti/k3-j7200-iG52m-common-proc-board.dts B/arch/arm64/boot/dts/ti/k3-j7200-iG52m-common-proc-board.dts
--- A/arch/arm64/boot/dts/ti/k3-j7200-iG52m-common-proc-board.dts 1970-01-01 05:30:00.000000000 +0530
+++ B/arch/arm64/boot/dts/ti/k3-j7200-iG52m-common-proc-board.dts 2026-01-23 11:33:37.086275754 +0530
@@ -0,0 +1,711 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024-2025 iwave Global Technologies Pvt Ltd.
+ */
+
+/dts-v1/;
+
+#include "k3-j7200-iG52m.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/mux/ti-serdes.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ };
+ aliases {
+ i2c0 = &wkup_i2c0;
+ i2c1 = &mcu_i2c0;
+ ethernet0 = &cpsw0_port3;
+ ethernet1 = &cpsw0_port2;
+ ethernet2 = &cpsw0_port1;
+ };
+
+
+
+
+
+ vdd_sd_dv: gpio-regulator-TLV71033 {
+ /* Output of TLV71033 */
+ compatible = "regulator-gpio";
+ regulator-name = "tlv71033";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_sd_dv_pins_default>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ gpios = <&wkup_gpio0 84 0>;
+ gpios-states = <0>;
+ states = <1800000 0x1>,
+ <3300000 0x0>;
+ };
+ iG52m_info {
+ compatible = "iwave Global,iG52m-info";
+ };
+};
+
+&wkup_pmx0 {
+ b7_pins_default: b7-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x8, PIN_OUTPUT, 2) /* (B7)*/
+ >;
+ };
+
+ som_eeprom_pins_default: som-eeprom-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 7) /*A8 eeprom write protect gpio for Som*/
+ >;
+ };
+
+ VU13p_pins_default_prog_pins_default: VU13p-pins-default-prog-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x28, PIN_OUTPUT, 7) /*WKUP_GPIO0_26*/
+ >;
+ };
+
+};
+
+
+&wkup_pmx1 {
+
+ d5_pins_default: d5-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 7) /* (D5)*/
+ >;
+ };
+};
+&wkup_pmx2 {
+ mcu_uart0_pins_default: mcu-uart0-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */
+ J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */
+ >;
+ };
+
+
+ main_10G_mdio_pins_default: main-10G-mdio-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (D9) MCU_MDIO0_MDC */
+ J721E_WKUP_IOPAD(0x30, PIN_INPUT, 0) /* (C9) MCU_MDIO0_MDIO */
+ >;
+ };
+
+ spi_pins_default: spi-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x58, PIN_INPUT, 0) /* (B18) WKUP_GPIO0_0.MCU_SPI1_CLK */
+ J721E_WKUP_IOPAD(0x5c, PIN_OUTPUT, 0) /* (B19) WKUP_GPIO0_1.MCU_SPI1_D0 */
+ J721E_WKUP_IOPAD(0x60, PIN_INPUT, 0) /* (D14) WKUP_GPIO0_2.MCU_SPI1_D1 */
+ J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (B21) WKUP_GPIO0_3.MCU_SPI1_CS0 */
+ >;
+ };
+ /*chipselect0: chipselect0-pins-defaul {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x64, PIN_INPUT, 0)
+ >;
+ };*/
+
+ vu_pmic2_pins_default: vu-pmic2-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /*A17*/
+ >;
+ };
+ ps_gpio_header_uart_pins_default: ps-gpio-header-uart-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x90, PIN_INPUT, 7) /*E20*/
+ J721E_WKUP_IOPAD(0x94, PIN_INPUT, 7) /*E21*/
+ >;
+ };
+
+ mcu_rgmii1_pins_default: mymcu_rgmii1-default-pins {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A9) MCU_RGMII1_RD0 */
+ J721E_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B9) MCU_RGMII1_RD1 */
+ J721E_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D10) MCU_RGMII1_TD0 */
+ J721E_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (B11) MCU_RGMII1_TD1 */
+ >;
+ };
+
+};
+
+&wkup_pmx3 {
+ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x1C, PIN_OUTPUT, 7) /*E18 */
+ >;
+ };
+};
+
+&main_pmx0 {
+ main_uart0_pins_default: main-uart0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */
+ J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
+ >;
+ };
+
+ VU13p_pins_default_done: VU13p-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xd8, PIN_INPUT, 7) /* (W2) MAIN_GPIO0_57 */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
+ J721E_IOPAD(0x100, PIN_OUTPUT, 0) /* (P21) MMC1_CLK */
+ J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
+ J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
+ J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
+ J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
+ J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
+ >;
+ };
+
+ main_cpsw_pins_default: main-cpsw-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x4c, PIN_INPUT, 4) /* (V19) MCAN5_RX.RGMII3_RD0 */
+ J721E_IOPAD(0x50, PIN_INPUT, 4) /* (T13) MCAN6_TX.RGMII3_RD1 */
+ J721E_IOPAD(0x54, PIN_INPUT, 4) /* (U14) MCAN6_RX.RGMII3_RD2 */
+ J721E_IOPAD(0x58, PIN_INPUT, 4) /* (U16) MCAN7_TX.RGMII3_RD3 */
+ J721E_IOPAD(0x48, PIN_INPUT, 4) /* (V21) MCAN5_TX.RGMII3_RXC */
+ J721E_IOPAD(0x5c, PIN_INPUT, 4) /* (U15) MCAN7_RX.RGMII3_RX_CTL */
+ J721E_IOPAD(0x60, PIN_OUTPUT, 4) /* (T15) MCAN8_TX.RGMII3_TD0 */
+ J721E_IOPAD(0x64, PIN_OUTPUT, 4) /* (U19) MCAN8_RX.RGMII3_TD1 */
+ J721E_IOPAD(0x68, PIN_OUTPUT, 4) /* (T14) MCAN9_TX.RGMII3_TD2 */
+ J721E_IOPAD(0x6c, PIN_OUTPUT, 4) /* (U18) MCAN9_RX.RGMII3_TD3 */
+ J721E_IOPAD(0x74, PIN_OUTPUT, 4) /* (U20) MCAN10_RX.RGMII3_TXC */
+ J721E_IOPAD(0x70, PIN_OUTPUT, 4) /* (U17) MCAN10_TX.RGMII3_TX_CTL */
+ >;
+ };
+ main_mdio_pins_default: main-mdio1-pins-default{
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xa8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */
+ J721E_IOPAD(0xa4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */
+ >;
+ };
+
+ eth_reset_pins_default: gpio0-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xd4, PIN_INPUT, 7) /* (V3) I2C0_SCL.GPIO0_56 */
+ >;
+ };
+ Eth_10G_reset_pins_default: Eth-10G-reset-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xE0, PIN_INPUT, 7) /* (T3)*/
+ >;
+ };
+
+ typec_irq_pins_default: typec-irq-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xc4, PIN_INPUT_PULLUP, 7) /* (U5) MAIN_GPIO0_52 */
+ >;
+ };
+
+ vu_pmic1_pins_default: vu-pmic1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1c, PIN_OUTPUT, 7) /*AA19*/
+ >;
+ };
+
+ RGMII2_pins_default: RGMII2-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x28, PIN_OUTPUT, 4) /*(W21) RGMII2_TXC/MCAN1_TX/RMII2_TX_EN/SPI6_CS0/EHRPWM_SOCA/GPMC0_A3/MCASP0_AXR11/GPIO0_11*/
+ J721E_IOPAD(0xa0, PIN_OUTPUT, 4) /*(U21) RGMII2_TX_CTL/GPIO0_41/RMII2_TXD0/SPI6_D1/UART4_RXD/GPMC0_A13/MCASP2_ACLKX */
+ J721E_IOPAD(0x90, PIN_OUTPUT, 4) /*(W17) RGMII2_TD0/MCAN15_TX/RMII2_RXD0/GPIO0_37/SPI6_CS2/EQEP1_S/GPMC0_CSN2/GPMC0_A0/GPMC0_A21/MCASP2_AXR1*/
+ J721E_IOPAD(0x94, PIN_OUTPUT, 4) /*(W20) RGMII2_TD1/MCAN15_RX/RMII2_RXD1/SPI6_CS3/EQEP1_I/GPMC0_A15/GPMC0_ADVN_ALE/GPIO0_38/MCASP2_AXR2 */
+ J721E_IOPAD(0x98, PIN_OUTPUT, 4) /*(V14) RGMII2_TD2/UART2_RXD/RMII2_CRS_DV/SPI6_CLK/GPMC0_CLKOUT/GPMC0_FCLK_MUX/OBSCLK2/GPIO0_39/MCASP2_AXR3*/
+ J721E_IOPAD(0x9c, PIN_OUTPUT, 4) /*(V13) RGMII2_TD3/UART2_TXD/RMII2_RX_ER/GPIO0_40/SPI6_D0/MCASP2_AFSX */
+ J721E_IOPAD(0x78, PIN_INPUT, 4) /*(Y14) RGMII2_RXC/MCAN11_TX/SPI2_CS0/EQEP0_A/SPI0_CS2/UART3_RXD/MCASP0_AXR13/GPMC0_A11/UART0_DTRN/GPIO0_31*/
+ J721E_IOPAD(0x8c, PIN_INPUT, 4) /*(AA16) RGMII2_RX_CTL/MCAN13_RX/GPMC0_CSN3/GPIO0_36/SPI2_D1/EQEP0_I/I2C5_SDA/UART8_RTSN/I3C0_SDA/GPMC0_A20/MCASP2_AXR0 */
+ J721E_IOPAD(0x7c, PIN_INPUT, 4) /*(Y13) RGMII2_RD0/MCAN11_RX/SPI2_CS1/EQEP0_B/UART3_TXD/MCASP0_AXR14/GPMC0_A12/UART0_RIN/GPIO0_32 */
+ J721E_IOPAD(0x80, PIN_INPUT, 4) /*(AA15) RGMII2_RD1/GPIO0_33/SPI2_CS2/EQEP1_A/I2C6_SCL/UART2_RXD/MCASP0_AXR15/GPMC0_BE1N/GPMC0_A17/MCAN12_TX */
+ J721E_IOPAD(0x84, PIN_INPUT, 4) /*(AA14) RGMII2_RD2/GPIO0_34/SPI2_CS3/EQEP1_B/I2C6_SDA/UART2_TXD/MCASP1_AXR8/I3C0_SDAPULLEN/GPMC0_A18/MCAN12_RX */
+ J721E_IOPAD(0x88, PIN_INPUT, 4) /*(AA18) RGMII2_RD3/MCAN13_TX/GPMC0_WPN/SPI2_D0/EQEP0_S/I2C5_SCL/UART8_CTSN/MCASP1_AXR9/I3C0_SCL/GPMC0_A19/GPIO0_35 */
+ >;
+ };
+
+ main_uart1_pins_default: main-uart1-default-pins {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xbc, PIN_OUTPUT, 0) /* (T20) UART1_TXD.MCAN17_RX */
+ J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD.MCAN17_TX */
+ >;
+ };
+ pcie_rst_pins_default: pcie-rst-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x44, PIN_INPUT, 7) /*Y20*/
+ >;
+ };
+ ps_gpio_header_pins_default: ps-gpio-header-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x20, PIN_INPUT, 7) /* (V18) MCAN0_TX.GPIO0_9 */
+ J721E_IOPAD(0x24, PIN_INPUT, 7) /* (V20) MCAN0_RX.GPIO0_10 */
+ J721E_IOPAD(0x38, PIN_INPUT, 7) /* (Y21) MCAN3_TX.GPIO0_15 */
+ J721E_IOPAD(0x3c, PIN_INPUT, 7) /* (W16) MCAN3_RX.GPIO0_16 */
+ >;
+ };
+};
+
+&main_pmx2 {
+ main_usbss0_pins_default: main-usbss0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
+ >;
+ };
+};
+
+&mcu_uart0 {
+ status = "okay";
+ /* Default pinmux */
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_uart0_pins_default>;
+};
+
+&main_uart0 {
+ status = "okay";
+ /* Shared with ATF on this platform */
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+};
+
+&main_uart1 {
+ status = "okay";
+ /* Default pinmux */
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
+
+};
+
+&main_uart2 {
+ /* MAIN UART 2 is used by R5F firmware */
+ status = "reserved";
+};
+
+
+&main_gpio0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <ð_reset_pins_default &Eth_10G_reset_pins_default &ps_gpio_header_pins_default &VU13p_pins_default_done>;
+ 10G_reset_gpio {
+ gpio-hog;
+ gpios = <59 GPIO_ACTIVE_HIGH>;
+ output-high;
+ linename = "10G_rst";
+ };
+};
+
+&main_gpio2 {
+ status = "disabled";
+};
+
+&main_gpio4 {
+ status = "disabled";
+};
+
+&main_gpio6 {
+ status = "disabled";
+};
+
+&wkup_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ps_gpio_header_uart_pins_default &VU13p_pins_default_prog_pins_default>;
+};
+
+&wkup_gpio1 {
+ status = "disabled";
+};
+
+&cpsw0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_rgmii1_pins_default>;
+};
+
+&davinci_mdio{
+
+ status = "disabled";
+
+};
+
+&mcu_cpsw{
+ status = "disabled";
+};
+
+&cpsw5g_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mdio_pins_default>;
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ compatible = "ethernet-phy-ieee802.3-c22";
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ device_type = "ethernet-phy";
+ host-in-si1;
+
+ };
+
+};
+
+
+&cpsw0_port3 {
+ status = "okay";
+ pinctrl-names = "default";
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy3>;
+ phys = <&cpsw0_phy_gmii_sel 3>;
+};
+
+&cpsw0_port1 {
+ status = "okay";
+ phy-mode = "usxgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 1>, <&serdes0_usxgmii_link>;
+ phy-names = "mac", "serdes";
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ };
+};
+
+&cpsw0_port2 {
+ status = "okay";
+ phy-mode = "rgmii";
+ phys = <&cpsw0_phy_gmii_sel 2>;
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&main_i2c0 {
+ status = "disabled";
+};
+&wkup_i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+ eeprom_osm: eeprom@54 {
+ status = "okay";
+ compatible = "atmel,24mac402";
+ reg = <0x54>;
+ pagesize = <16>;
+ address-width = <8>;
+ size = <256>;
+ };
+ i2c_mux: msd9548@73 {
+ compatible = "nxp,pca9548";
+ reg = <0x73>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ i2c@1{
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ ioexp3gpio: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&ioexp2gpio>;
+ interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+ label = "ioexp3gpio";
+ usb_power{
+ gpio-hog;
+ gpios = <12 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+ };
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ };
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ ioexp1gpio: gpio@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <52 IRQ_TYPE_EDGE_FALLING>;
+ label = "ioexp1gpio";
+ qsfp_1_top {
+ gpio-hog;
+ gpios = <0 0>;
+ output-low;
+ };
+ qsfp_1_bottom {
+ gpio-hog;
+ gpios = <5 0>;
+ output-low;
+ };
+ };
+ ioexp2gpio: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ interrupt-parent = <&ioexp1gpio>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+ label = "ioexp2gpio";
+ qsfp_2_top {
+ gpio-hog;
+ gpios = <0 0>;
+ output-low;
+ };
+ qsfp_2_bottom {
+ gpio-hog;
+ gpios = <5 0>;
+ output-low;
+ };
+ };
+ fusb302: typec-portc@22 {
+ compatible = "fcs,fusb302";
+ pinctrl-names = "default";
+ pinctrl-0 = <&typec_irq_pins_default>;
+ reg = <0x22>;
+ fcs,int_n = <&ioexp3gpio 15 IRQ_TYPE_EDGE_FALLING>;
+ status = "okay";
+ };
+ dp159: hdmi-retimer@5b {
+ status = "okay";
+ compatible = "ti,dp159";
+ reg = <0x5b>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <0>;
+ };
+ };
+ };
+};
+
+&mcu_i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tmp442@4c {
+ compatible = "ti,tmp442";
+ reg = <0x4c>;
+ };
+ eeprom_som: eeprom@52 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&som_eeprom_pins_default>;
+ status = "okay";
+ compatible = "atmel,24mac402";
+ reg = <0x52>;
+ pagesize = <16>;
+ address-width = <8>;
+ size = <256>;
+ };
+ eeprom_Carrier_board: eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ address-width = <8>;
+ size = <512>;
+ };
+
+
+
+ vu13_pmic_1: vu13_da9062@48 {
+ compatible = "dlg,da9062";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vu_pmic1_pins_default>;
+ reg = <0x48>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "okay";
+
+ gpio {
+ compatible = "dlg,da9062-gpio";
+ };
+ };
+
+ vu13_pmic_2: vu13_da9062@58 {
+ compatible = "dlg,da9062";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vu_pmic2_pins_default>;
+ reg = <0x58>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "okay";
+
+ gpio {
+ compatible = "dlg,da9062-gpio";
+ };
+ };
+
+
+
+};
+&mcu_i2c1 {
+
+ status = "disabled";
+};
+
+&main_sdhci0 {
+ status = "okay";
+ /* eMMC */
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_sdhci1 {
+ status = "okay";
+ /* SD card */
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ pinctrl-names = "default";
+ vqmmc-supply = <&vdd_sd_dv>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+ bus-width = <4>;
+};
+
+&serdes_ln_ctrl {
+ status = "okay";
+ idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
+ <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
+};
+
+
+&usb_serdes_mux {
+ idle-states = <1>; /* USB0 to SERDES lane 3 */
+};
+
+&usbss0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ ti,vbus-divider;
+ ti,usb2-only;
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+ phy-names = "cdns3,usb2-phy";
+};
+
+&tscadc0 {
+ adc {
+ ti,adc-channels = <0 1 2 3 4 5 6 7>;
+ };
+};
+
+&serdes_refclk {
+ clock-frequency = <100000000>;
+};
+
+
+&serdes_wiz0 {
+ status = "okay";
+};
+&serdes0 {
+ status = "okay";
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
+ };
+
+ serdes0_usxgmii_link: phy@1 {
+ reg = <2>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USXGMII>;
+ resets = <&serdes_wiz0 3>;
+ };
+};
+
+&pcie1_rc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_rst_pins_default>;
+ reset-gpios = <&main_gpio0 18 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <2>;
+};
+
+
+
+#define K3_TS_OFFSET(pa, val) (0x4+(pa)*4) (0x10000 | val)
+
+×ync_router {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_cpsw_cpts>;
+
+ /* Use Time Sync Router to map GENF1 input to HW4_TS_PUSH output */
+ mcu_cpsw_cpts: mcu-cpsw-cpts {
+ pinctrl-single,pins = <
+ /* pps [mcu cpsw cpts genf1] in17 -> out25 [mcu cpsw cpts hw4_push] */
+ K3_TS_OFFSET(25, 17)
+ >;
+ };
+};
+
+
+&mcu_spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_pins_default>;
+ ti,spi-num-cs = <1>;
+ ti,pindir-d0-out-d1-in;
+ spi-sram@0 {
+ compatible = "microchip,mchp23a512";
+ reg = <0x0>;
+ spi-max-frequency = <16000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "okay";
+ };
+};
diff -Naur --no-dereference A/arch/arm64/boot/dts/ti/k3-j7200-iG52m.dtsi B/arch/arm64/boot/dts/ti/k3-j7200-iG52m.dtsi
--- A/arch/arm64/boot/dts/ti/k3-j7200-iG52m.dtsi 1970-01-01 05:30:00.000000000 +0530
+++ B/arch/arm64/boot/dts/ti/k3-j7200-iG52m.dtsi 2025-11-10 16:44:31.690406405 +0530
@@ -0,0 +1,297 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024-2025 iwave Global Technologies Pvt Ltd.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "k3-j7200.dtsi"
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ /* 2G RAM */
+ reg = <0x00 0x80000000 0x00 0x80000000>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@a4000000 {
+ reg = <0x00 0xa4000000 0x00 0x00800000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+ vsys_3v3: fixedregulator-vsys3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcca_5v: fixedregulator-vcca5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+};
+
+&wkup_pmx0 {
+ pmic_irq_pins_default: pmic-irq-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (U6) WKUP_GPIO0_0 */
+ >;
+ };
+};
+
+&wkup_pmx2 {
+ /* wkup_pmx2 starts at 0x68 */
+ wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
+ J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
+ >;
+ };
+};
+&hbmc {
+ status = "disabled";
+};
+
+&mailbox0_cluster0 {
+ status = "okay";
+ interrupts = <436>;
+
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mailbox0_cluster1 {
+ status = "okay";
+ interrupts = <432>;
+
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
+};
+
+&mcu_r5fss0_core0 {
+ status = "okay";
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
+ memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
+ <&mcu_r5fss0_core0_memory_region>;
+};
+
+&mcu_r5fss0_core1 {
+ status = "okay";
+ mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
+ memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
+ <&mcu_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_i2c0 {
+
+};
+
+&ospi0 {
+ status = "disabled";
+};
+
+&wkup_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_i2c0_pins_default>;
+ clock-frequency = <400000>;
+
+ tps659414: pmic@48 {
+ compatible = "ti,tps6594-q1";
+ reg = <0x48>;
+ ti,primary-pmic;
+ system-power-controller;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_irq_pins_default>;
+ interrupt-parent = <&wkup_gpio0>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ buck1-supply = <&vcca_5v>;
+ buck2-supply = <&vcca_5v>;
+ buck3-supply = <&vcca_5v>;
+ buck4-supply = <&vcca_5v>;
+ buck5-supply = <&vcca_5v>;
+ ldo1-supply = <&vsys_3v3>;
+ ldo2-supply = <&vsys_3v3>;
+ ldo3-supply = <&vsys_3v3>;
+ ldo4-supply = <&vsys_3v3>;
+
+ regulators {
+ bucka1: buck1 {
+ regulator-name = "vda_mcu_1v8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ bucka2: buck2 {
+ regulator-name = "vdd_mcuio_1v8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ bucka3: buck3 {
+ regulator-name = "vdd_mcu_0v85";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ bucka4: buck4 {
+ regulator-name = "vdd_ddr_1v1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ bucka5: buck5 {
+ regulator-name = "vdd_phyio_1v8";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa1: ldo1 {
+ regulator-name = "vdd1_lpddr4_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa2: ldo2 {
+ regulator-name = "vda_dll_0v8";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa3: ldo3 {
+ regulator-name = "vdd_wk_0v8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldoa4: ldo4 {
+ regulator-name = "vda_pll_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+};
+&main_mcan0 {
+ status = "disabled";
+};
diff -Naur --no-dereference A/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi B/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
--- A/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi 2025-11-03 10:14:31.636501044 +0530
+++ B/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi 2026-01-21 10:09:46.710046757 +0530
@@ -5,6 +5,7 @@
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/phy/phy-ti.h>
/ {
serdes_refclk: serdes-refclk {
#clock-cells = <0>;
@@ -400,16 +401,36 @@
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
+/*IG52M fix for EVK bug*/
+ main_pmx1: pinctrl@11c110 {
- main_pmx1: pinctrl@11c11c {
compatible = "ti,j7200-padconf", "pinctrl-single";
/* Proxy 0 addressing */
- reg = <0x00 0x11c11c 0x00 0xc>;
+ reg = <0x00 0x11c110 0x00 0x004>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
+ main_pmx2: pinctrl@11c11c {
+ compatible = "ti,j7200-padconf", "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x11c11c 0x00 0x00c>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ main_pmx3: pinctrl@11c164 {
+ compatible = "ti,j7200-padconf", "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x11c164 0x00 0x008>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
@@ -635,7 +656,6 @@
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
- mmc-hs400-1_8v;
dma-coherent;
};
@@ -663,56 +683,37 @@
};
serdes_wiz0: wiz@5060000 {
- compatible = "ti,j721e-wiz-10g";
+ compatible = "ti,j7200-wiz-10g";
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
- clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>, <&k3_clks 292 89>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
num-lanes = <4>;
#reset-cells = <1>;
- ranges = <0x5060000 0x0 0x5060000 0x10000>;
+ ranges;
+ #clock-cells = <1>;
+ ti,scm = <&scm_conf>;
assigned-clocks = <&k3_clks 292 85>;
- assigned-clock-parents = <&k3_clks 292 89>;
-
- wiz0_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 292 85>, <&serdes_refclk>;
- clock-output-names = "wiz0_pll0_refclk";
- #clock-cells = <0>;
- assigned-clocks = <&wiz0_pll0_refclk>;
- assigned-clock-parents = <&k3_clks 292 85>;
- };
-
- wiz0_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 292 85>, <&serdes_refclk>;
- clock-output-names = "wiz0_pll1_refclk";
- #clock-cells = <0>;
- assigned-clocks = <&wiz0_pll1_refclk>;
- assigned-clock-parents = <&k3_clks 292 85>;
- };
-
- wiz0_refclk_dig: refclk-dig {
- clocks = <&k3_clks 292 85>, <&serdes_refclk>;
- clock-output-names = "wiz0_refclk_dig";
- #clock-cells = <0>;
- assigned-clocks = <&wiz0_refclk_dig>;
- assigned-clock-parents = <&k3_clks 292 85>;
- };
-
- wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
- clocks = <&wiz0_refclk_dig>;
- #clock-cells = <0>;
- };
+ assigned-clock-parents = <&k3_clks 292 88>;
+ assigned-clock-rates = <156250000>;
serdes0: serdes@5060000 {
- compatible = "ti,j721e-serdes-10g";
+ compatible = "ti,j7200-serdes-10g";
reg = <0x05060000 0x00010000>;
reg-names = "torrent_phy";
resets = <&serdes_wiz0 0>;
reset-names = "torrent_reset";
- clocks = <&wiz0_pll0_refclk>;
- clock-names = "refclk";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>;
+ clock-names = "refclk", "refclk1";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 292 85>,
+ <&k3_clks 292 89>,
+ <&k3_clks 292 85>;
#address-cells = <1>;
#size-cells = <0>;
};
diff -Naur --no-dereference A/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi B/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
--- A/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi 2025-11-03 10:14:31.637501099 +0530
+++ B/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi 2025-12-05 09:39:12.611363030 +0530
@@ -315,7 +315,7 @@
clocks = <&k3_clks 274 0>;
status = "disabled";
};
-
+/*IG52M fix SPI crash*/
mcu_spi1: spi@40310000 {
compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
reg = <0x00 0x040310000 0x00 0x400>;
@@ -323,7 +323,7 @@
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 275 0>;
+ clocks = <&k3_clks 275 4>;
status = "disabled";
};
diff -Naur --no-dereference A/arch/arm64/boot/dts/ti/Makefile B/arch/arm64/boot/dts/ti/Makefile
--- A/arch/arm64/boot/dts/ti/Makefile 2025-11-03 10:14:31.638501155 +0530
+++ B/arch/arm64/boot/dts/ti/Makefile 2025-11-10 16:44:31.736407012 +0530
@@ -81,6 +81,8 @@
dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm-mcspi-loopback.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm-virt-mac-client.dtbo
+#Boards with DRA821Ux IG52M Platform
+dtb-$(CONFIG_ARCH_K3) += k3-j7200-iG52m-common-proc-board.dtb
# Boards with J721e SoC
k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb
Thanks and Regards,
Subashini
HI,
We are using an x16 Endpoint PCIe. If I remove theserdes0_pcie_linknode, will it affect the Endpoint PCIe functionality?
Do I need to remove this node to validate the 10G configuration
SerDes support multi functions as PCIe + USXGMII.
If you want PCIe along with USXGMII, need to enable both links from SerDes.
SerDes configuration from above device tree looks fine for enabling PCIe + USXGMII.
When you are using multi function like PCIe + USXGMII you need to use two reference clocks for SerDes 100MHz for PCIe and 156.25MHz for USXGMII.
Best Regards,
Sudheer