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TDA4VH-Q1: LSDK 9.2 Linux native driver USXGMII unable to ping issue

TD LI
Prodigy 20 points

Part Number: TDA4VH-Q1

Hi expert
   LSDK9.2  serdes2 lane2 and lane3

I am using the TI LSDK9.2 kernel with k3-j784s4-evm-usxgmii-exp1-exp2 (device tree overlay). I only modified the fixed-link configuration block in k3-j784s4-evm-usxgmii-exp1-exp2 from:
fixed-link {
                 speed = <5000>;
                 full-duplex;
};
to
fixed-link {
               speed = <10000>;
full-duplex;
};
without making any changes to the kernel.
The USXGMII interface fails to achieve ping connectivity in this setup.
However, when I enable ETHFW on MCU2-0, the USXGMII interface becomes pingable.

demsg log 
k3conf dump clock 406  and the value of register 0x0502e000.
 
oot@j784s4-evm:~# ethtool  eth1
Settings for eth1:
        Supported ports: [ MII ]
        Supported link modes:   10000baseCR/Full
        Supported pause frame use: Symmetric Receive-only
        Supports auto-negotiation: Yes
        Supported FEC modes: Not reported
        Advertised link modes:  10000baseCR/Full
        Advertised pause frame use: Symmetric
        Advertised auto-negotiation: Yes
        Advertised FEC modes: Not reported
        Link partner advertised link modes:  10000baseCR/Full
        Link partner advertised pause frame use: No
        Link partner advertised auto-negotiation: No
        Link partner advertised FEC modes: Not reported
        Speed: 10000Mb/s
        Duplex: Full
        Auto-negotiation: on
        Port: MII
        PHYAD: 0
        Transceiver: internal
        Supports Wake-on: d
        Wake-on: d
        Current message level: 0x000020f7 (8439)
                               drv probe link ifdown ifup rx_err tx_err hw
        Link detected: yes
root@j784s4-evm:~# dmesg | grep eth
[    0.000000] psci: probing for conduit method from DT.
[    1.035905] optee: probing for conduit method.
[    1.458173] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[    1.471024] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[    1.478232] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[    1.488514] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:1
[    1.498348] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA03102, cpsw version 0x6BA82902 Ports: 9 quirks:00000000
[    2.358172] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[    2.371039] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[    2.378247] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[    2.388529] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:1
[    2.398428] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
[    2.406090] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA03102, cpsw version 0x6BA82902 Ports: 9 quirks:00000000
[    2.419980] am65-cpsw-nuss c000000.ethernet: Use random MAC address
[    2.426297] am65-cpsw-nuss c000000.ethernet: Use random MAC address
[    2.432570] am65-cpsw-nuss c000000.ethernet: initialized cpsw ale version 1.5
[    2.439689] am65-cpsw-nuss c000000.ethernet: ALE Table size 512
[    2.445890] am65-cpsw-nuss c000000.ethernet: CPTS ver 0x4e8a010c, freq:250000000, add_val:3 pps:0
[    2.456995] am65-cpsw-nuss c000000.ethernet: set new flow-id-base 82
[    2.899241] systemd[1]: /etc/systemd/system/sync-clocks.service:11: Standard output type syslog is obsolete, automatically updating to journal. Please update your unit file, and consider removing the s.
[    6.146165] am65-cpsw-nuss c000000.ethernet eth2: configuring for fixed/usxgmii link mode
[    6.154388] am65-cpsw-nuss c000000.ethernet eth2: Link is Up - 10Gbps/Full - flow control off
[    6.164276] am65-cpsw-nuss c000000.ethernet eth1: configuring for fixed/usxgmii link mode
[    6.173071] am65-cpsw-nuss c000000.ethernet eth1: Link is Up - 10Gbps/Full - flow control off
[    6.180081] IPv6: ADDRCONF(NETDEV_CHANGE): eth2: link becomes ready
[    6.192490] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
root@j784s4-evm:~# [   18.349060] platform regulator-dp0-prw: deferred probe pending
[   18.354910] platform regulator-dp1-prw: deferred probe pending
[   18.360733] platform regulator-sd: deferred probe pending
[   18.366123] platform dp0-connector: deferred probe pending
[   18.371596] platform 4fb0000.mmc: deferred probe pending
[   18.376895] platform 4a00000.dss: deferred probe pending

root@j784s4-evm:~# k3conf dump clock 406
|------------------------------------------------------------------------------|
| VERSION INFO                                                                 |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Wed Mar 06 14:29:58 UTC 2024)              |
| SoC    | J784S4 SR1.0                                                        |
| SYSFW  | ABI: 3.1 (firmware version 0x0009 '9.0.6--v09.00.06 (Kool Koala))') |
|------------------------------------------------------------------------------|

|----------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name                                                            | Status          | Clock Frequency |
|----------------------------------------------------------------------------------------------------------------------------------|
|   406     |     2    | DEV_SERDES_10G2_CLK                                                   | CLK_STATE_READY | 125000000       |
|   406     |     3    | DEV_SERDES_10G2_CMN_REFCLK_M                                          | CLK_STATE_READY | 0               |
|   406     |     3    | DEV_SERDES_10G2_CMN_REFCLK_M                                          | CLK_STATE_READY | 0               |
|   406     |     4    | DEV_SERDES_10G2_CMN_REFCLK_P                                          | CLK_STATE_READY | 0               |
|   406     |     5    | DEV_SERDES_10G2_CORE_REF1_CLK                                         | CLK_STATE_READY | 156250000       |
|   406     |     6    | DEV_SERDES_10G2_CORE_REF_CLK                                          | CLK_STATE_READY | 156250000       |
|   406     |     7    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT           | CLK_STATE_READY | 19200000        |
|   406     |     8    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT            | CLK_STATE_READY | 0               |
|   406     |     9    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 156250000       |
|   406     |    10    | DEV_SERDES_10G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000       |
|   406     |    12    | DEV_SERDES_10G2_IP1_LN0_REFCLK                                        | CLK_STATE_READY | 0               |
|   406     |    13    | DEV_SERDES_10G2_IP1_LN0_RXCLK                                         | CLK_STATE_READY | 0               |
|   406     |    14    | DEV_SERDES_10G2_IP1_LN0_RXFCLK                                        | CLK_STATE_READY | 0               |
|   406     |    15    | DEV_SERDES_10G2_IP1_LN0_TXCLK                                         | CLK_STATE_READY | 0               |
|   406     |    16    | DEV_SERDES_10G2_IP1_LN0_TXFCLK                                        | CLK_STATE_READY | 0               |
|   406     |    17    | DEV_SERDES_10G2_IP1_LN0_TXMCLK                                        | CLK_STATE_READY | 0               |
|   406     |    18    | DEV_SERDES_10G2_IP1_LN1_REFCLK                                        | CLK_STATE_READY | 0               |
|   406     |    19    | DEV_SERDES_10G2_IP1_LN1_RXCLK                                         | CLK_STATE_READY | 0               |
|   406     |    20    | DEV_SERDES_10G2_IP1_LN1_RXFCLK                                        | CLK_STATE_READY | 0               |
|   406     |    21    | DEV_SERDES_10G2_IP1_LN1_TXCLK                                         | CLK_STATE_READY | 0               |
|   406     |    22    | DEV_SERDES_10G2_IP1_LN1_TXFCLK                                        | CLK_STATE_READY | 0               |
|   406     |    23    | DEV_SERDES_10G2_IP1_LN1_TXMCLK                                        | CLK_STATE_READY | 0               |
|   406     |    24    | DEV_SERDES_10G2_IP1_LN2_REFCLK                                        | CLK_STATE_READY | 0               |
|   406     |    25    | DEV_SERDES_10G2_IP1_LN2_RXCLK                                         | CLK_STATE_READY | 0               |
|   406     |    26    | DEV_SERDES_10G2_IP1_LN2_RXFCLK                                        | CLK_STATE_READY | 0               |
|   406     |    27    | DEV_SERDES_10G2_IP1_LN2_TXCLK                                         | CLK_STATE_READY | 0               |
|   406     |    28    | DEV_SERDES_10G2_IP1_LN2_TXFCLK                                        | CLK_STATE_READY | 0               |
|   406     |    29    | DEV_SERDES_10G2_IP1_LN2_TXMCLK                                        | CLK_STATE_READY | 0               |
|   406     |    30    | DEV_SERDES_10G2_IP1_LN3_REFCLK                                        | CLK_STATE_READY | 0               |
|   406     |    31    | DEV_SERDES_10G2_IP1_LN3_RXCLK                                         | CLK_STATE_READY | 0               |
|   406     |    32    | DEV_SERDES_10G2_IP1_LN3_RXFCLK                                        | CLK_STATE_READY | 0               |
|   406     |    33    | DEV_SERDES_10G2_IP1_LN3_TXCLK                                         | CLK_STATE_READY | 0               |
|   406     |    34    | DEV_SERDES_10G2_IP1_LN3_TXFCLK                                        | CLK_STATE_READY | 0               |
|   406     |    35    | DEV_SERDES_10G2_IP1_LN3_TXMCLK                                        | CLK_STATE_READY | 0               |
|   406     |    48    | DEV_SERDES_10G2_IP2_LN2_REFCLK                                        | CLK_STATE_READY | 0               |
|   406     |    49    | DEV_SERDES_10G2_IP2_LN2_RXCLK                                         | CLK_STATE_READY | 0               |
|   406     |    50    | DEV_SERDES_10G2_IP2_LN2_RXFCLK                                        | CLK_STATE_READY | 0               |
|   406     |    51    | DEV_SERDES_10G2_IP2_LN2_TXCLK                                         | CLK_STATE_READY | 0               |
|   406     |    52    | DEV_SERDES_10G2_IP2_LN2_TXFCLK                                        | CLK_STATE_READY | 0               |
|   406     |    53    | DEV_SERDES_10G2_IP2_LN2_TXMCLK                                        | CLK_STATE_READY | 0               |
|   406     |    54    | DEV_SERDES_10G2_IP2_LN3_REFCLK                                        | CLK_STATE_READY | 0               |
|   406     |    55    | DEV_SERDES_10G2_IP2_LN3_RXCLK                                         | CLK_STATE_READY | 0               |
|   406     |    56    | DEV_SERDES_10G2_IP2_LN3_RXFCLK                                        | CLK_STATE_READY | 0               |
|   406     |    57    | DEV_SERDES_10G2_IP2_LN3_TXCLK                                         | CLK_STATE_READY | 0               |
|   406     |    58    | DEV_SERDES_10G2_IP2_LN3_TXFCLK                                        | CLK_STATE_READY | 0               |
|   406     |    59    | DEV_SERDES_10G2_IP2_LN3_TXMCLK                                        | CLK_STATE_READY | 0               |
|   406     |   129    | DEV_SERDES_10G2_TAP_TCK                                               | CLK_STATE_READY | 0               |
|----------------------------------------------------------------------------------------------------------------------------------|

root@j784s4-evm:~# devmem2 0x0502e000
/dev/mem opened.
Memory mapped at address 0xffffb4d58000.
Read at address  0x0502E000 (0xffffb4d58000): 0x00490051
 
Best Regards, 
 TD



  • 0
    TI__Guru* 75880 points

    Hi,

    TD LI said:
    However, when I enable ETHFW on MCU2-0, the USXGMII interface becomes pingable.

    When you switched to the ETHFW application instead of the Native Linux driver, able to ping with USXGMII 10G.

    TD LI said:
    without making any changes to the kernel.
    The USXGMII interface fails to achieve ping connectivity in this setup.

    Can you please confirm whether you can ping with 5Gbps?

    By default, the "drivers/phy/ti/phy-j721e-wiz.c" has a configuration for 5Gbps.

    Enabling a 10G link requires the following change from the "wiz_mode_select" API under USXGMII PHY TYPE.

    - ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3);
- mode = LANE_MODE_GEN1;
+ ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x2);
+ mode = LANE_MODE_GEN2;


    I recommend first checking the ping with 5Gbps. If it works, make the above suggested changes and check for 10Gbps.


    Best Regards,
    Sudheer
  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 20 points

    Hi Doredla

    10Gb USXGMII can already ping successfully. Thank you.
    Can another lane within the same SerDes as USXGMII support XAUI at 2.5 Gbps?
    &main_cpsw0_port6 {
    status = "okay";
    phy-mode = "sgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_sgmii_link>;
    phy-names = "mac", "serdes";
    fixed-link {
        speed = <2500>;
        full-duplex;
    };
};

serdes2_sgmii_link: phy@1 {
    reg = <1>;
    cdns,num-lanes = <1>;
    #phy-cells = <0>;
    cdns,phy-type = <PHY_TYPE_SGMII>;
    resets = <&serdes_wiz2 2>;
};
    How can I enable 2.5 Gbps support in Linux native?
    Best Regards,
    TD
  • 0 in reply to TD LI
    TI__Guru* 75880 points

    Hi, 

    TD LI said:
    10Gb USXGMII can already ping successfully. Thank you

    Thank you for confirming 10G ping is working. Is it with above my suggestion or by default? 

    TD LI said:
    Can another lane within the same SerDes as USXGMII support XAUI at 2.5 Gbps?

    SerDes IP supports for multi-function of USXGMII + XAUI but, no configuration support from driver. 

    Current driver don't have support for XAUI 2.5G configuration. 

    Best Regards, 

    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 70 points

    Hi Doredla

    With the patch you provided, 10G ping is working.
    If USXGMII + XAUI is not supported, does it support USXGMII + SGMII (1Gb)?
    I need to make this port work with either XAUI or SGMII.
    What should I do?
    Best Regards,
    TD
  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 70 points

    Hi Doredla

    On the same SerDes, lanes 2/3 are configured for USXGMII at 10G, and lane 1 is intended for XAUI at 2.5G.
    In the Linux native driver, both XAUI and USXGMII use the same reference clock of 156.25 MHz—the only difference being the link rate:
    • USXGMII operates at 10.3125 Gbps
    • XAUI operates at 3.125 Gbps
    Is it possible to modify the existing USXGMII configuration to support XAUI instead?

    Best Regards,
    TD

        

  • 0 in reply to guangjun yang
    TI__Guru* 75880 points

    Hi,

    guangjun yang said:
    If USXGMII + XAUI is not supported, does it support USXGMII + SGMII (1Gb)?

    USXGMII + SGMII will be a supported configuration.

    guangjun yang said:
    In the Linux native driver, both XAUI and USXGMII use the same reference clock of 156.25 MHz—the only difference being the link rate:
    • USXGMII operates at 10.3125 Gbps
    • XAUI operates at 3.125 Gbps
    Is it possible to modify the existing USXGMII configuration to support XAUI instead?

    Even though USXGMII and XAUI use the same reference clock of 156.25 MHz, the lane settings for XAUI are different, and it may not be an easy change.

    As USXGMII + SGMII works for you, you can go ahead with this configuration, as it is already supported.

    If you need further support on any other topic, please create a new thread. 

    Best Regards,
    Sudheer