Part Number: TMS320C6657
Hi E2E team,
We would like to have your support on one issue that we’re having on the PCI Express link training in between our FPGA XC7A200T-2FBG676I and DSP from TI TMS320C6657 :
We have already conducted several SW and HW tests, but we still have the problem persisting in our table:
Basically, we are doing 1000 reboots to test the link training in between the FPGA and the DSP chip and around 20 out of 1000 reboots we have problem in the link training for the 5Gbps.
Our procedure it’s that we have the handshake in between DSP <-> FPGA and then we start the link training at 2.5Gbps and when we have that asserted, we switch to the 5Gbps and it’s only during this last step that we have the issue.
Basically, we can assert 1000 times after reboot the handshake and the 2,5Gbps always without problems.
- Problem only when we change from 2.5G to 5G
We have checked all the errata’s from TMS chip regarding the Reset sequencing, and we are covering everything.
This behavior it’s something that you’ve experienced or are you aware of it? There is something that you can share with us?
Thank you.
