J721EXCPXEVM: cold boot vs warm boot

Hi,

Mandy Liu said:

I checked the manual, CTRLMMR_WKUP_RESET_SRC_STAT 4300 0050h seems like the correct register. But when I read the value of the register from u-boot cmdline or early in spl stage, I found the value is not as what I expected:
When power cycle or reboot from linux, the value shows 0

During power cycle it will be 0.
In case of Linux reboot issuing a power reset to SoC by PMIC still it shows 0.

Mandy Liu said:

When reset from u-boot, the value shows 1.

In case of U-boot, it appears to be reset will be performed by issuing a SW reset to SoC, resulting a value of 1 captured in RESET_SRC register.

Mandy Liu said:

I would like to know how to know it is a power cycle or reboot from linux.

Need to check the kind of reset issued to SoC from Linux and update to a different method such as toggle RESET PIN of SoC if connected to PMIC instead of power reset.


Best Regards,
Sudheer

But I still need to know the difference between watchdog reset vs power reset, since we will use main watchdog to monitor linux, so in case of any system hang and watchdog reset the device, we still need to a way to know it is not a power cycle. Or any register we can use to write a cookie and can be kept while power watchdog reboot? I tried K3_MCU_SCRATCHPAD, but that part of memory will be cleared while watchdog reboot.
Any other suggestion?

Regards,
Mandy

Hi, 

If watchdog reset driving event signal to PMIC for SoC reset, based on reset mechanism used by PMIC, reset src status reflects in SoC. 

Let me also check internally once. 

Best Regards, 

Sudheer

Hi Sudheer,

I can confirm that when watchdog reset the device, the 0x43000050 value is 0.

Best regards,

Mandy 

Hi Sudheer,

I confirm that when watchdog reset the device the 0x43000050 value is 0.

Best regards,

Mandy

Hi,

We have tried on our side as well, the result is as follows.

reset at U-Boot -> Force reset issuing via triggering Software MCU reset (both Main and MCU domains gets reset) - > 0x43000050 value is 1.
reboot at Linux - > same result as reset as U-Boot -> 0x43000050 value is 1.

Watchdog from Linux -> trigger an event signal to PMIC issuing SoC reset -> 0x43000050 value is 0.

Watchdog is unintended trigger whereas reset or reboot is interntional controlled by ATF issuing a softreset.

Best Regards,
Sudheer

I understand. My question is:
Watchdog from Linux -> trigger an event signal to PMIC issuing SoC reset -> 0x43000050 value is 0.
In this case, is there a way I can tell the SoC reset is done by watchdog instead of power cycle since in both case 0x43000050 value is 0?

Best regards,
Mandy

Hi,

Mandy Liu said:

Watchdog from Linux -> trigger an event signal to PMIC issuing SoC reset -> 0x43000050 value is 0.
In this case, is there a way I can tell the SoC reset is done by watchdog instead of power cycle since in both case 0x43000050 value is 0?

We don't have a mechanism to differentiate a a watchdog reset and a power cycle, as both reflect the same value in the RESET_SRC register.

Best Regards,
Sudheer