AM6422: How to do ddrss multi bits test under uboot2023.10 - inline ECC

xixiguohx

Part Number: AM6422

Hi TI Experts,

We are using AM6422 customized boards. I want to do the inline ECC ddrss test.

I have enabled the inline ECC accordding to https://software-dl.ti.com/processor-sdk-linux-rt/esd/AM64X/11_02_08_02/exports/docs/linux/Foundational_Components/U-Boot/UG-DDRSS.html

2. And followed https://git.ti.com/cgit/ti-u-boot/ti-u-boot/commit/?h=ti-u-boot-2023.04-next&id=af5609db6d1124e046cf623f80e00c3d27ff5fec to compile the ddrss cmd in uboot.

When I did the ddrss test, 1bit error behavior is the same with the describe of the Release Notes.

=> ddrss ecc_err 82400000 1
Testing DDR ECC:
        ECC test: Disabling DDR ECC ...
        ECC test: addr 0x82400000, read data 0x0, written data 0x1, err pattern: 0x1, read after write data 0x1
        ECC test: Enabled DDR ECC ...
        ECC test: addr 0x82400000, read data 0x0
        ECC test: DDR ECC 1-bit error
        ECC test: 1-bit ECC err count: 1
        ECC test: 1-bit error in [0x2400000:0x2400008]
=> ddrss ecc_err 82400000 1
Testing DDR ECC:
        ECC test: Disabling DDR ECC ...
        ECC test: addr 0x82400000, read data 0x1, written data 0x0, err pattern: 0x1, read after write data 0x0
        ECC test: Enabled DDR ECC ...
        ECC test: addr 0x82400000, read data 0x0
=>

But the multi bit error and multiple single bit error behavior are different.

=> ddrss ecc_err 82400000 3
Testing DDR ECC:
        ECC test: Disabling DDR ECC ...
        ECC test: addr 0x82400000, read data 0x0, written data 0x3, err pattern: 0x3, read after write data 0x3
        ECC test: Enabled DDR ECC ...

ERROR:   Unhandled External Abort received on 0x80000000 from EL2
ERROR:   exception reason=1 syndrome=0x92000210
Unhandled Exception from EL2
x0             = 0x0000000000000001
x1             = 0x0000000000000000
x2             = 0x000000000000000a
x3             = 0x0000000002800000
x4             = 0x0000000002800000
x5             = 0x00000000986724df
x6             = 0x0000000000000033
x7             = 0x000000000000000f
x8             = 0x0000000098672920
x9             = 0x00000000fffffff0
x10            = 0x0000000000000010
x11            = 0x0000000000000002
x12            = 0x0000000000000002
x13            = 0x0000000098672c10
x14            = 0x00000000ffffffff
x15            = 0x00000000986724df
x16            = 0x000000009a6ebed4
x17            = 0x0000000000000000
x18            = 0x0000000098686d90
x19            = 0x0000000000000004
x20            = 0x0000000082400000
x21            = 0x000000000000023f
x22            = 0x0000000000000000
x23            = 0x0000000000000003
x24            = 0x0000000000000000
x25            = 0x0000000000000000
x26            = 0x000000000f300134
x27            = 0x0000000000001a7f
x28            = 0x00000000986dd440
x29            = 0x0000000098672920
x30            = 0x000000009a6ec118
scr_el3        = 0x000000000000073d
sctlr_el3      = 0x0000000030cd183f
cptr_el3       = 0x0000000000000000
tcr_el3        = 0x0000000080803520
daif           = 0x00000000000002c0
mair_el3       = 0x00000000004404ff
spsr_el3       = 0x00000000600002c9
elr_el3        = 0x000000009a6ec118
ttbr0_el3      = 0x00000000701ce800
esr_el3        = 0x0000000092000210
far_el3        = 0x0000000082400000
spsr_el1       = 0x0000000000000000
elr_el1        = 0x0000000000000000
spsr_abt       = 0x0000000000000000
spsr_und       = 0x0000000000000000
spsr_irq       = 0x0000000000000000
spsr_fiq       = 0x0000000000000000
sctlr_el1      = 0x0000000030d00801
actlr_el1      = 0x0000000000000000
cpacr_el1      = 0x0000000000000000
csselr_el1     = 0x0000000000000000
sp_el1         = 0x0000000000000000
esr_el1        = 0x0000000000000000
ttbr0_el1      = 0x0000000000000000
ttbr1_el1      = 0x0000000000000000
mair_el1       = 0x0000000000000000
amair_el1      = 0x0000000000000000
tcr_el1        = 0x0000000000800080
tpidr_el1      = 0x0000000000000000
tpidr_el0      = 0x0000000000000000
tpidrro_el0    = 0x0000000000000000
par_el1        = 0x0000000000000000
mpidr_el1      = 0x0000000080000000
afsr0_el1      = 0x0000000000000000
afsr1_el1      = 0x0000000000000000
contextidr_el1 = 0x0000000000000000
vbar_el1       = 0x0000000000000000
cntp_ctl_el0   = 0x0000000000000000
cntp_cval_el0  = 0x0000000000000000
cntv_ctl_el0   = 0x0000000000000000
cntv_cval_el0  = 0x0000000000000000
cntkctl_el1    = 0x0000000000000000
sp_el0         = 0x00000000701cb400
isr_el1        = 0x0000000000000000
dacr32_el2     = 0x0000000000000000
ifsr32_el2     = 0x0000000000000000
cpuectlr_el1   = 0x0000000000000040
cpumerrsr_el1  = 0x00000000011c0316
l2merrsr_el1   = 0x0000000013082800
cpuactlr_el1   = 0x00001000090ca000

=> ddrss ecc_err 82400000 1
Testing DDR ECC:
        ECC test: Disabling DDR ECC ...
        ECC test: addr 0x82400000, read data 0x0, written data 0x1, err pattern: 0x1, read after write data 0x1
        ECC test: Enabled DDR ECC ...
        ECC test: addr 0x82400000, read data 0x0
        ECC test: DDR ECC 1-bit error
        ECC test: 1-bit ECC err count: 1
        ECC test: 1-bit error in [0x2400000:0x2400008]
=> ddrss ecc_err 82400008 1
Testing DDR ECC:
        ECC test: Disabling DDR ECC ...
        ECC test: addr 0x82400008, read data 0x0, written data 0x1, err pattern: 0x1, read after write data 0x1
        ECC test: Enabled DDR ECC ...

ERROR:   Unhandled External Abort received on 0x80000000 from EL2
ERROR:   exception reason=1 syndrome=0x92000210
Unhandled Exception from EL2
x0             = 0x0000000000000001
x1             = 0x0000000000000000
x2             = 0x000000000000000a
x3             = 0x0000000002800000
x4             = 0x0000000002800000
x5             = 0x00000000986724df
x6             = 0x0000000000000031
x7             = 0x000000000000000f
x8             = 0x0000000098672920
x9             = 0x00000000fffffff0
x10            = 0x0000000000000010
x11            = 0x0000000000000002
x12            = 0x0000000000000002
x13            = 0x0000000098672c10
x14            = 0x00000000ffffffff
x15            = 0x00000000986724df
x16            = 0x000000009a6ebed4
x17            = 0x0000000000000000
x18            = 0x0000000098686d90
x19            = 0x0000000000000004
x20            = 0x0000000082400008
x21            = 0x000000000000023f
x22            = 0x0000000000000000
x23            = 0x0000000000000001
x24            = 0x0000000000000000
x25            = 0x0000000000000000
x26            = 0x000000000f300134
x27            = 0x0000000000001a7f
x28            = 0x00000000986dd440
x29            = 0x0000000098672920
x30            = 0x000000009a6ec118
scr_el3        = 0x000000000000073d
sctlr_el3      = 0x0000000030cd183f
cptr_el3       = 0x0000000000000000
tcr_el3        = 0x0000000080803520
daif           = 0x00000000000002c0
mair_el3       = 0x00000000004404ff
spsr_el3       = 0x00000000600002c9
elr_el3        = 0x000000009a6ec118
ttbr0_el3      = 0x00000000701ce800
esr_el3        = 0x0000000092000210
far_el3        = 0x0000000082400008
spsr_el1       = 0x0000000000000000
elr_el1        = 0x0000000000000000
spsr_abt       = 0x0000000000000000
spsr_und       = 0x0000000000000000
spsr_irq       = 0x0000000000000000
spsr_fiq       = 0x0000000000000000
sctlr_el1      = 0x0000000030d00801
actlr_el1      = 0x0000000000000000
cpacr_el1      = 0x0000000000000000
csselr_el1     = 0x0000000000000000
sp_el1         = 0x0000000000000000
esr_el1        = 0x0000000000000000
ttbr0_el1      = 0x0000000000000000
ttbr1_el1      = 0x0000000000000000
mair_el1       = 0x0000000000000000
amair_el1      = 0x0000000000000000
tcr_el1        = 0x0000000000800080
tpidr_el1      = 0x0000000000000000
tpidr_el0      = 0x0000000000000000
tpidrro_el0    = 0x0000000000000000
par_el1        = 0x0000000000000000
mpidr_el1      = 0x0000000080000000
afsr0_el1      = 0x0000000000000000
afsr1_el1      = 0x0000000000000000
contextidr_el1 = 0x0000000000000000
vbar_el1       = 0x0000000000000000
cntp_ctl_el0   = 0x0000000000000000
cntp_cval_el0  = 0x0000000000000000
cntv_ctl_el0   = 0x0000000000000000
cntv_cval_el0  = 0x0000000000000000
cntkctl_el1    = 0x0000000000000000
sp_el0         = 0x00000000701cb400
isr_el1        = 0x0000000000000000
dacr32_el2     = 0x0000000000000000
ifsr32_el2     = 0x0000000000000000
cpuectlr_el1   = 0x0000000000000040
cpumerrsr_el1  = 0x00000000001c0356
l2merrsr_el1   = 0x0000000013082940
cpuactlr_el1   = 0x00001000090ca000

Can you help to check why the Multi bit error and Multiple single bit error behavior are different from what the Release Notes describes?

Thank you!

1 month ago

0 Bin Liu 1 month ago

TI__Guru**** 175641 points

Hi,

Can you please confirm you use the U-Boot version provided in the SDK v11.02 package?

0 xixiguohx 1 month ago in reply to Bin Liu

Intellectual 730 points

Hi Bin,

It's not the U-Boot version in SDK v11.02. Is there any huge different about the inline-ECC parts between these two versions?

Could you please help to check that if I missed any configures or code changes about enable inline-ECC?

And below is the memory mapping in my u-boot,

My DDR size is 512M. I think the optee part should be out of the ECC region. Because it's a fixed load/entry address 0x9e800000. So the rest DDR size is 0x80000000 ~ 0x9e7fffff(If enabled inline ECC, 1/9 of this part should be reserved as ECC data storage). And I think all the ECC data is stored at the end of the rest DDR. Is my understanding correct?

Thank you!

xixiguo

0 Bin Liu 1 month ago in reply to xixiguohx

TI__Guru**** 175641 points

Hi Xixiguo,

xixiguohx said:
It's not the U-Boot version in SDK v11.02. Is there any huge different about the inline-ECC parts between these two versions?

I need to know the U-Boot version you use, so that we are communicating on the same code base.

xixiguohx said:
And I think all the ECC data is stored at the end of the rest DDR. Is my understanding correct?

No, the ECC data are in-line, 64 bytes ECC are stored in-line after every 512 bytes data.

0 xixiguohx 1 month ago in reply to Bin Liu

Intellectual 730 points

Hi Bin,

My u-boot version is u-boot2023.10, thank you.

Bin Liu said:
No, the ECC data are in-line, 64 bytes ECC are stored in-line after every 512 bytes data.

If the 512B was followed by 64B of ECC data, do we need to consider avoiding writing to the area of ECC data when accessing memory? Or does inline-ECC handle the address issue for us, and we can just access memory addresses normally and consecutively?

xixiguo

0 Bin Liu 1 month ago in reply to xixiguohx

TI__Guru**** 175641 points

Hi Xixiguo,

xixiguohx said:
Or does inline-ECC handle the address issue for us, and we can just access memory addresses normally and consecutively?

Yes this is the case. It is that the total memory size for software is 8/9 of the total DDR size.

By the way, I didn't try configuring DDR size to be 512MB on AM64x EVM, but I am not sure how you are able to get to the U-Boot cmdline prompt, but if you check the reserved-memory node in devicetree k3-am642-evm.dts or k3-am642-sk.dtsi, the address of most reserved memory regions there are above 0xa000-0000, which is beyond 512MB. I don't think you can run Linux on AN64x with only 512MB DDR, regardless DDR ECC is enabled or not.

0 xixiguohx 1 month ago in reply to Bin Liu

Intellectual 730 points

Hi Bin,

We modified the dts of tiboot3.bin and u-boot.img, changed the memory mapping. And we did not use the R5 cores after Linux bootup. So the memory regions which are using above 0xa000-0000 are not enabled.

Could you kindly help to check that if we can enable the inline ECC in u-boot2023.10?

xixiguo

0 Bin Liu 1 month ago in reply to xixiguohx

TI__Guru**** 175641 points

Hi Xixiguo,

I don't think we tried to run 512MB DDR for AM64x, let me try this on AM64x EVM to see if I can reproduce the issue then I will look into it.

I have a few work in the pipeline, I will try to get into this test probably by middle of next week.

0 Bin Liu 8 days ago in reply to Bin Liu

TI__Guru**** 175641 points

Hi Xixiguo,

Sorry I haven't got time to test this on EVM yet, but just wanted to check if you still need support for this query?

0 xixiguohx 7 days ago in reply to Bin Liu

Intellectual 730 points

Hi Bin,

I still need support for this query, thank you!

xixguo

0 Bin Liu 7 days ago in reply to xixiguohx

TI__Guru**** 175641 points

Hi Xixiguo,

It sounds like you ported the DDR ECC function to U-Boot 2023.10. Have you tried the U-Boot provided in SDK11.02 to see if the issue still exists?

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AM6422: How to do ddrss multi bits test under uboot2023.10 - inline ECC