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DRA829V: DDR initialization procedure

Antonio Pinto
Prodigy 160 points

Part Number: DRA829V

Dear TI team,

We are reviewing the DDR initialization procedure and would like clarification on the following points.

The TRM describes several sections related to the complete DDR initialization flow:

  • 8.2.4.6.9 DDR Controller Initialization
  • 8.2.4.7.5 DDR PHY Initialization
  • 8.2.4.8.1 PI Initialization
  • 8.2.4.5 DDRSS Dynamic Frequency Change Interface
  1. When comparing these TRM sections with the PDK implementation, we noticed that steps from the different chapters appear to be interleaved. Could you confirm whether this behavior is intentional?
  2. Register settings generated by ‘Jacinto 7 DDRSS Register Configuration Tool’ (SPRACU8) already set the DDRSS_PI_139[8] PI_DRAM_INIT_EN bit to 0x1. Is this configuration sufficient, or should this bit be explicitly set again during initialization?
  3. The TRM does not reference DDRSS_PLL_FHS_CNT, but PDK repeats the DDR initiated frequency change sequence for DDRSS_PLL_FHS_CNT times. Can you confirm whether this repetition is always required by the implementation?

Thank you in advance.

Best regards,
António

  • 0
    TI__Mastermind 41480 points

    Hi,

    Customers should use the DDR drivers provided in SPL / SBL and not create their own. We provide a DDR configuration tool that allows customers to customize settings in case of using a different memory. 

    Antonio Pinto said:
    but PDK repeats the DDR initiated frequency change sequence for DDRSS_PLL_FHS_CNT times. Can you confirm whether this repetition is always required by the implementation?

    Yes, switching frequencies is a fundamental principle of LPDDR4 command bus training. 

    Regards,
    Kevin

  • 0 in reply to Kevin S
    Prodigy 160 points

    Hi Kevin,
    Thanks for your reply.

    Kevin S said:
    Customers should use the DDR drivers provided in SPL / SBL and not create their own. We provide a DDR configuration tool that allows customers to customize settings in case of using a different memory. 

    Actually, we are using the same sequence as provided in the PDK and generating the register settings from ‘Jacinto 7 DDRSS Register Configuration Tool’ (SPRACU8).
    However, due to certification purposes we need to clarify the sequence steps.

    Antonio Pinto said:
    • 8.2.4.6.9 DDR Controller Initialization
    • 8.2.4.7.5 DDR PHY Initialization
    • 8.2.4.8.1 PI Initialization
    • 8.2.4.5 DDRSS Dynamic Frequency Change Interface

    So, each chapter mentioned above describes its own sequence.
    Since some steps from these chapters are mixed in the implementation, can you please clarify if it is intended?

    Thank you.
    António