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AM625: OSPI read throughput efficency

Tony Tang
Mastermind 29862 points

Part Number: AM625
Other Parts Discussed in Thread: SK-AM62B-P1

Customer needs to attach FPGA to SOC with data throughput up to 85MByte/s. Consider GPMC throughput is not enough from many customer's use case, so developed OSPI+FPGA. 

#1. As the FPGA capability can't support up to 166MHz OSPI PHY mode clock. how to adjust it to 100MHz which can be supported by FPGA on custom board?

#2. When OSPI PHY mode works at 100MHz, can the READ operation throughput achieve 85MByte/s? 

#3.  Why the throughput are quite different between SK board and P1 board, both boards use same OSPI NOR flash S28HS512TGABHM010

 https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/11_02_08_02/exports/docs/devices/AM62X/linux/Linux_Performance_Guide.html#linux-ospi-flash-driver

image.png

BTW, in PHY mode, the OSPI_CLK is 166MHz, how can it achieve 170.77Mbyte/sec?

  • 0
    TI__Expert 7290 points

    Hello Tony,

    I will let our OSPI driver expert Vaibhav comment on the above documented mismatches in speed performance of OSPI Raw Flash Driver between  SK-AM62X and SK-AM62B-P1 EVMs.

    Tony Tang said:
    BTW, in PHY mode, the OSPI_CLK is 166MHz, how can it achieve 170.77Mbyte/sec?

    As far as I know it operates in PHY DDR mode with data tuning. So actually it should theoretically achieve 2*166MHz = 332 MBytes / sec ignoring the command and address portion of the OSPI to NOR Flash protocol.

    So Vaibhav, do you have any assumptions on the 177.77MByte/sec measurement at 166 MHz  - is it an average value that in some way considers the command / response overhead ? 

    Thanks

    Best Regards,

    Anastas Yordanov

  • 0 in reply to Anastas Yordanov
    TI__Mastermind 29862 points
    Anastas Yordanov said:
    As far as I know it operates in PHY DDR mode with data tuning. So actually it should theoretically achieve 2*166MHz = 332 MBytes / sec ignoring the command and address portion of the OSPI to NOR Flash protocol.

    In DDR PHY mode, support minimum 19ns clock cycle time only, a little above 50MHz.

  • 0 in reply to Tony Tang
    TI__Expert 7290 points

    Hi Tony,

    I agree, but shown above is PHY DDR without data training 

    OSPI0 PHY DDR with data training (I think also called data tuning):

    Thanks

    Best Regards

    Anastas

  • 0
    TI__Guru 53663 points

    Hi Tony,

    Tony Tang said:
    #3.  Why the throughput are quite different between SK board and P1 board, both boards use same OSPI NOR flash S28HS512TGABHM010

    The difference is observed, because the AM62x-SK has a OSPI NOR S28HS512T flash part, whereas the AM62x-SK-LP variant has a OSPI NAND Flash W35Nxxxx.

    Regarding the throughput, I will have another expert comment on it, as we have some measurements ready to be shared(Note, this will be rolled out as an application note).

    Regards,

    Vaibhav

  • 0
    TI__Prodigy 240 points

    Hi Tony,

    I have benchmarked the Flash operations for MCU+ SDK. Please refer the numbers below:



    Flash: Serial NOR OSPI Flash (S28HS512T)

    Input Clock Frequency : 200MHz , Input Clock Division: 4

    Protocol: 8D-8D-8D

    Data Size: 10 MB

    Data Size PHY DMA INDAC Writes DAC Reads Erase
    10 MB Yes Yes 0.46 MBps 332.20 MBps 0.31 MBps

    Flash: Serial NAND OSPI Flash (W35N01JWTBAG)

    Input Clock Frequency : 166MHz , Input Clock Division: 8

    Protocol: 1S-8S-8S

    Data Size: 10 MB

    Data Size PHY DMA DAC Writes DAC Reads Erase
    10 MB Yes Yes 1.70 MBps 46.68 MBps 149.28 MBps
  • 0 in reply to Aryamaan Chaurasia
    TI__Mastermind 29862 points

    So the reads efficiency can be up to 332.2/400=83% with OSPI NOR flash in 8D-8D-8D DDR mode.

  • 0 in reply to Tony Tang
    TI__Prodigy 240 points
    Tony Tang said:
    So the reads efficiency can be up to 332.2/400=83% with OSPI NOR flash in 8D-8D-8D DDR mode.

    Yes, that is correct