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DRA829J: OSPI PHY mode with training

Dmitry Tuykov
Expert 1261 points

Part Number: DRA829J
Other Parts Discussed in Thread: DRA829

Dear TI-Team,

We're currently using DRA829 OSPI0 interface in QSPI mode together with 2x MT25QL02G flash chips in SDR mode with TAP and frequency of 50 MHz. To improve performance we think about using PHY mode with training and higher frequencies (~90 MHz), but stil SDR.

To mitigate potential risks, I would like to clarify with you couple of questions:

  • Has any other customer used the described above configuration with PHY mode and training? Can we expect potential risks here with lack of documentation, code examples, TI support?
  • Is there any dependency of the training on the env. temperature, in other words, is it required to repeat the procedure periodically? 
  • We've noticed SPRACT2 document, but it describes training in DDR mode, is there anything similar for SDR? It refer to code for Linux, is there any alternative code example in PDK/SDK?
  • What's a typical duration of the training procedure?
  • Do we get it right, that SDR/TAP mode is limited with 50 MHz at max?

And one more general question: do you see anything else we need to pay attention to considering use of PHY mode + training?

Thanks,
Dmitry

 

 

  • 0
    TI__Mastermind 41750 points

    Hi,

    Dmitry Tuykov said:
    Do we get it right, that SDR/TAP mode is limited with 50 MHz at max?

    Dmitry Tuykov said:
    Has any other customer used the described above configuration with PHY mode and training? Can we expect potential risks here with lack of documentation, code examples, TI support?

    I don't think I am aware from Jacinto side if any customer has used this mode. But let me check up with Sitara colleagues. Those devices also use the same OSPI controller. However, the components are independently configurable and should not pose an issue from configuration standpoint. However this is not the mode on which signals are characterised. So testing will be lacking.

    Dmitry Tuykov said:
    Is there any dependency of the training on the env. temperature, in other words, is it required to repeat the procedure periodically? 

    The training is temperature dependent. If being used for longer duration with different SOC temp, there will be a need to rerun the training.

    Dmitry Tuykov said:
    We've noticed SPRACT2 document, but it describes training in DDR mode, is there anything similar for SDR? It refer to code for Linux, is there any alternative code example in PDK/SDK?

    SDR mode can be enabled in both PDK and SDK

    Dmitry Tuykov said:
    • What's a typical duration of the training procedure?

    I will check this and let you know

    Dmitry Tuykov said:
    Do we get it right, that SDR/TAP mode is limited with 50 MHz at max?

    Yes, the TAP+SDR mode works only at 50MHz max.

    Regards,
    Tanmay

  • 0 in reply to Tanmay Patil
    Expert 1261 points

    Hello Tanmay,

    have you had a chance to check the mode with Sitara colleagues?

    Another question I would like to address is clock configuration. We currently use OSPI_HCLK = 1000 / 3 = 333 MHz (pretty standard value) and OSPI_RCLK = 200 MHz, which by using internal OSPI divider helps us to obtain 50 MHz on SPI transmit/receive logic. 

    Are you aware of any constraints to these clocks in PHY mode?

    Thanks,
    Dmitry