TDA4VM: LWIP example not working on SK-TDA4VM

Hi,

The PSDK RTOS support for the SK-TDA4VM board is not available. It has only a Linux package.

If you would like to use PSDK RTOS for SK-TDA4VM, you need to make board-specific changes to the examples, as this SDK is developed for the Common Processor Board (https://www.ti.com/tool/J721EXCPXEVM) +  SOM (https://www.ti.com/tool/J721EXSOMXEVM).

Best Regards,
Sudheer

 Doredla Sudheer Kumar , 
Would you please highlight the expected changes, I need to make it to work? 
Like, pin configurations, clock configurations or anything else I need to make. 

I was compiling the FW using the j721e_evm as board for core mcu2_1. 

Thanks,
Muhammad Usman

Hi,

PHY is detected by MDIO, I believe clock is supplied.

Can you please check whether  "Cpsw_periodicTick" API is called or not?  I could not see Link up here eventhough PHY is detected.

Best Regards,
Sudheer

Hi Doredla Sudheer Kumar ,

Yes the Cpsw_periodicTick is calling properly. 

The link status variable (linkStatus) is always  "ENETPHY_LINK_DOWN". 

Thanks,
Muhammad Usman

Hi,

Muhammad Usman said:

The link status variable (linkStatus) is always  "ENETPHY_LINK_DOWN". 

It means PHY is not Link Up. Can you please read the PHY BMSR register and check whether the link is up or not? 

Also, can you please confirm that CPSW is disabled from HLOS (Linux)?  
Also, ensure PHY is Link Up.


Best Regards,
Sudheer

 Hi Doredla Sudheer Kumar , 

The BMSR shows that link is down. 
I am not running HLOS. Just FreeRTOS on MCU2_1 using CCS workflow (launch.js runs first, then reset the CPU core and then LWIP example app on MCU2_1). 

PHY always remains in ENETPHY_FSM_STATE_NWAY_WAIT state, until the timeouts and state machine restarted. 
I increased the timeout but same behavior. 

Thanks,

Muhammad Usman

HI, 

Muhammad Usman said:

The BMSR shows that link is down

It means PHY side no Link Up with link partner.

Muhammad Usman said:

I am not running HLOS. Just FreeRTOS on MCU2_1 using CCS workflow (launch.js runs first, then reset the CPU core and then LWIP example app on MCU2_1)

Understood, just running using CCS. 

Muhammad Usman said:

PHY always remains in ENETPHY_FSM_STATE_NWAY_WAIT state, until the timeouts and state machine restarted. 
I increased the timeout but same behavior

It would be due to no link-up from phy side. 

Have you verified data transfer from CPSW 2G when loading Linux? 

Best Regards 

Sudheer

Hi,

Yes I can see proper link up messages on Linux and DHCP works on Linux. 

Thanks,

Muhammad Usman

Hi,

Muhammad Usman said:

Yes I can see proper link up messages on Linux and DHCP works on Linux. 

Understood.

I have verified the Linux device tree for SK-EVM. I could not see any additional GPIOs used for PHY control.

Can you please confirm whether Pinmux is configured for MCU CPSW2G as RGMII?
Also, please share the list of changes applied to the ENET LWIP example.

Best Regards,
Sudheer

Hi,

I added some log starting with "TRACE:". Only four lines below which shows that PINMUX is fine. 

==========================
Enet lwIP App
==========================
TRACE: Configuring MCU CPSW2G MAC mode=2 (RGMII=2)
TRACE: MCU_ENET_CTRL register written with value=0x12
EnetBoard_setupPorts: 1 of 1 ports configurations found
TRACE: Configuring MCU RGMII pinmux (moduleId=5)
TRACE: MCU RGMII pinmux configuration completed
CPU Load: 39%
Starting lwIP, local interface IP is dhcp-enabled
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:0 From 1 To 0
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:1 From 1 To 0
EnetMcm: CPSW_2G on MCU NAVSS
Mdio_open: MDIO manual mode enabled
PHY 0 is alive
EnetPhy_bindDriver: PHY 0: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK
Host MAC address: 34:08:e1:59:db:e4
[LWIPIF_LWIP] Enet LLD netif initialized successfully
status_callback==UP, local interface IP is 0.0.0.0
CPU Load: 6%
CPU Load: 2%
CPU Load: 2%
CPU Load: 2%

The only change I did in file (.../enet_lwip_example/test_config_j721e.c) is: 
#define APP_ENABLE_STATIC_CFG                      (0U)    ---->     #define APP_ENABLE_STATIC_CFG                      (1U)

Thanks,

Muhammad Usman

Hi,

Muhammad Usman said:

TRACE: Configuring MCU CPSW2G MAC mode=2 (RGMII=2)
TRACE: MCU_ENET_CTRL register written with value=0x12
EnetBoard_setupPorts: 1 of 1 ports configurations found
TRACE: Configuring MCU RGMII pinmux (moduleId=5)
TRACE: MCU RGMII pinmux configuration completed
CPU Load: 39%

If so, Pins are mapped to RGMII.

You supposed to get PHY Link Up if its connected with Link partner.

Best Regards,
Sudheer

Hi,

Unfortunately the link is not establishing. As soon the code runs the LEDs on RJ45 connector turn OFF, before running the example they are ON. 

Best regards,

Muhammad Usman

Hi,

Muhammad Usman said:

Unfortunately the link is not establishing. As soon the code runs the LEDs on RJ45 connector turn OFF, before running the example they are ON. 

Can you please check if PHY is bootstrapped? If so, you can ignore the PHY configuration in the CPSW MAC Port configuration and use phyaddr ENETPHY_INVALID_PHYADDR, as captured below.

Best Regards,
Sudheer

Hi, 

Setting ENETPHY_INVALID_PHYADDR didn't work. 

Moreover, I did some debugging and observed that the Ethernet LEDs turn OFF as soon as the following function executes even I do not run the LWIP example:

void SciApp_consoleInit(void)
{
    Board_initCfg   boardCfg;

    boardCfg = BOARD_INIT_PINMUX_CONFIG |
               BOARD_INIT_UART_STDIO;
    Board_init(boardCfg);
}

Simply load the launch.js file and run that code using CCS instead of resetting the core1_0.
If I remove the BOARD_INIT_PINMUX_CONFIG from above code it keeps LEDs in ON state. 

So I am suspecting that there is some problem in PIN configurations. I'll investigate it further in LWIP example and get back to you on it. 

Thanks,

Muhammad Usman