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nand read speed issue

jiang lv
Prodigy 110 points

Hi,Marc

I encounter the nand read speed issue during my development, the detail
procedure as below:

1.I used the Micron Large page x16 NAND for development.

2.In \u-boot-2010.06-psp04.00.00.10\arch\arm\include\asm\arch-ti81xx\Mem.h
file , I modified the M_NAND_GPMC_CONFIG5 bit 0-4(which means RDCYCLETIME).
from 1e(default) to 07(fast speed as calculated) .

3.I print the value of M_NAND_GPMC_CONFIG5 ,lt's vaule changed as i
modified.

4. I through Oscilloscope I observed  between both setting(1e and 07)
TOE(which means read cycle time) are around 632 ns.looks like the change
doesn't take the effect for the hardware.

whether any other setting i need to do to solve this issue?

  • 0
    TI__Mastermind 25055 points

    Hello,

    I have asked our PSP team to take a look at this.

    Regards,
    Marc

  • 0 in reply to MarcPyne
    Prodigy 110 points

    Hi Marc,

    Any update?

    lvjiang

  • 0 in reply to jiang lv
    Prodigy 105 points

    Hi Jiang,

    I too ran into this issue with u-boot, but after lots of reading and fiddling I have managed to get my read speeds up to 7.3MB/s.

    The main improvement came from enabling the L2, L1 caches, which seem to have been missed.

    Unfortunately to enable the L1 D cache and the L2 unified cache, you have to also enable the MMU, which u-boot doesn't have support for yet.

    Then also you can gain a decent speed increase by actually watching the wait pin after a READ0 command rather than just waiting 100us as is currently done.

    Then if you are using ECC error correction, you can skip asking for error location info from the ELM by checking if the "calc_ecc" array consists of just 0s, (that means there were no errors).

    Finally it's not just the RDCYCLETIME configuration variable that needs modifying. Most of the defaults need changing.

    Hope that points you in the right direction,

    Andrew