Is a reference clock on the SERDES_CLK input required for SATA operation only (no PCIe)?
In the DM8148 datasheet, it says under 8.18.2 "A standard 100-MHz differential clock source must be used for SATA operation (for details, see Section 7.4.2, SERDES_CLKN/P Input Clock)."
But in section 7.4.2, it says "A high-quality, low-jitter differential clock source is required for the PCIE PHY and is an optional clock source for the SATA PHY.".
Additionally, the TRM says under 2.3.6 "The SATA SERDES could optionally use the external 100 MHz reference as well. ... If the clock is not present, then using the DEVOSC 20 MHz reference for SATA SERDES is another solution."
Which one is correct?
