DRA829J: DDR PI initialization process

Antonio Pinto

Part Number: DRA829J

Dear TI team,

We are currently checking PI initialization process described in the TRM, chapter 8.2.4.8.1 PI Initialization.

Could you please confirm whether the step "3. Enable the DDR controller" is directly connected with the sequence described in the chapter 8.2.4.6.9 DDR Controller Initialization?

Thank you.
António

14 hours ago

0 Kevin S 12 hours ago

TI__Mastermind 40510 points

Hi,

"Enable the DDR controller" from chapter 8.2.4.8.1 (SPRUIL1D) is referring to setting the START bit of the controller (item #3 from chapter 8.2.4.6.9).

Please refer to the driver function "lpddr4_startsequencecontroller" which sets the PI_START bit of the PI, and then the START bit of the Controller. The respective START bits should only be set after the registers have been programmed and the hardware initialization / training sequence can begin.

https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/drivers/ram/k3-ddrss/lpddr4.c?h=11.02.11#n97

static u32 lpddr4_startsequencecontroller(const lpddr4_privatedata *pd)
{
	u32 result = 0U;
	u32 regval = 0U;
	lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
	lpddr4_infotype infotype;

	regval = CPS_FLD_SET(LPDDR4__PI_START__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_START__REG)));
	CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_START__REG)), regval);

	regval = CPS_FLD_SET(LPDDR4__START__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__START__REG)));
	CPS_REG_WRITE(&(ctlregbase->LPDDR4__START__REG), regval);

	if (pd->infohandler != (lpddr4_infocallback)NULL) {
		infotype = LPDDR4_DRV_SOC_PLL_UPDATE;
		pd->infohandler(pd, infotype);
	}

	result = lpddr4_pollandackirq(pd);

	return result;
}

Regards,
Kevin

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DRA829J: DDR PI initialization process