AM625: AM625 SPI0 chip select 1 doesn't work

Hi Robert,
What is the output of the command that you run on the console?

Hi Divyansh Mittal ,

Please  see output

root@buildroot:~$ spidev_test -D /dev/spidev2.1 -s 7000000 -v -p '1234567'
spi mode: 0x0
bits per word: 8
max speed: 7000000 Hz (7000 kHz)
TX | 31 32 33 34 35 36 37 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __  |1234567|
RX | 00 00 00 00 00 00 00 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __  |.......|
root@buildroot:~$ spidev_test -D /dev/spidev2.1 -s 7000000 -v -p '1234567'
spi mode: 0x0
bits per word: 8
max speed: 7000000 Hz (7000 kHz)
TX | 31 32 33 34 35 36 37 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __  |1234567|
RX | FF FF FF FF FF FF FF __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __  |.......|

Please noted that, I did not setup loopback MOSI vs MISO

Hi Robert,
Can you try changing 'PIN_INPUT' to 'PIN_OUTPUT' for CLK and CS1 and check if you are able to see the signals on probe?

Hi Divyansh Mittal ,

No luck

Hi Robert,
Can you please review your board schematics once and check that you are probing pins according to following at your end:

And also do cross check that you are not probing the MCU domain SPI0, but the MAIN domain SPI0.
If the issue still persists, I'll try replicating your setup at my end.

Hi Divyansh Mittal ,

Please see the snapshot of schematic:

another observation is SPI2 also gets same issue to SPI0

	main_spi2_pins_default: main-spi2-default-pins {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x01b0, PIN_OUTPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */
			AM62X_IOPAD(0x01ac, PIN_OUTPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */
			AM62X_IOPAD(0x0194, PIN_INPUT, 1) /* (B19) MCASP0_AXR3.SPI2_D0 */
			AM62X_IOPAD(0x0198, PIN_INPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */
		>;
	};

&main_spi2 {
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-0 = <&main_spi2_pins_default>;
	pinctrl-names = "default";
	ti,pindir-d0-out-d1-in;

	spidev@0 {
		/*
		 * Using spidev compatible is warned loudly,
		 * thus use another equivalent compatible id
		 * from spidev.
		 */
		compatible = "rohm,dh2228fv";
		spi-max-frequency = <12000000>;
		reg = <0>;
	};

};

I also recall about this issue:  AM625: DSS pixel clock can't set less than 15937500 Hz , please help to check if they have same root cause 

Hi Robert,
Thanks for the confirmation. The issue you mentioned was resolved in 10.1 SDK. Are you still using 9.02?

yes, it's being 9.02

Okay, I'll try reproduce the issue at my end, will respond my mid-next week.

Hi Robert,
I have tested at my side with main_spi0 and main_spi2 (don't have main_spi1 exposed on TI EVM) and I see the signals with 9.02 SDK:

diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts
index f9b7fa2e8156..beb8862374b9 100644
--- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts
@@ -133,6 +133,24 @@ vdd_core: regulator-8 {
 };
 
 &main_pmx0 {
+	main_spi0_pins_default: main-spi0-pins-default {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01bc, PIN_INPUT, 0) /* (A14) SPI0_CLK */
+			AM62X_IOPAD(0x01c0, PIN_INPUT, 0) /* (B13) SPI0_D0 */
+			AM62X_IOPAD(0x01c4, PIN_INPUT, 0) /* (B14) SPI0_D1 */
+			AM62X_IOPAD(0x01b8, PIN_INPUT, 0) /* (A13) SPI0_CS1 */
+		>;
+	};
+
+	main_spi2_pins_default: main-spi2-pins-default {
+		pinctrl-single,pins = <
+			AM62X_IOPAD(0x01b0, PIN_INPUT, 1) /* (A20) SPI2_CLK */
+			AM62X_IOPAD(0x0194, PIN_INPUT, 1) /* (B19) SPI2_D0 */
+			AM62X_IOPAD(0x0198, PIN_INPUT, 1) /* (A19) SPI2_D1 */
+			AM62X_IOPAD(0x01a4, PIN_INPUT, 1) /* (B20) SPI2_CS1 */
+		>;
+	};
+
 	main_rgmii2_pins_default: main-rgmii2-pins-default {
 		pinctrl-single,pins = <
 			AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
@@ -232,6 +250,17 @@ exp1: gpio@22 {
 	};
 };
 
+&main_i2c1 {
+	gpio@22 {
+		en_main_spi2 {
+			gpio-hog;
+			gpios = <21 GPIO_ACTIVE_HIGH>;
+			output-low;
+			line-name = "UART1_FET_SEL";
+		};
+	};
+};
+
 &sdhci1 {
 	vmmc-supply = <&vdd_mmc1>;
 	vqmmc-supply = <&vdd_sd_dv>;
@@ -347,6 +376,46 @@ partition@3fc0000 {
 	};
 };
 
+&main_spi0 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-0 = <&main_spi0_pins_default>;
+	pinctrl-names = "default";
+	ti,spi-num-cs = <2>;
+	ti,pindir-d0-out-d1-in;
+	spidev@1 {
+		/*
+		 * Using spidev compatible is warned loudly,
+		 * thus use another equivalent compatible id
+		 * from spidev.
+		 */
+		compatible = "rohm,dh2228fv";
+		spi-max-frequency = <7000000>;
+		reg = <1>;
+	};
+};
+
+&main_spi2 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-0 = <&main_spi2_pins_default>;
+	pinctrl-names = "default";
+	ti,spi-num-cs = <2>;
+	ti,pindir-d0-out-d1-in;
+	spidev@1 {
+		/*
+		 * Using spidev compatible is warned loudly,
+		 * thus use another equivalent compatible id
+		 * from spidev.
+		 */
+		compatible = "rohm,dh2228fv";
+		spi-max-frequency = <7000000>;
+		reg = <1>;
+	};
+};
+
 &tlv320aic3106 {
 	DVDD-supply = <&vcc_1v8>;
 };
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c2f0cf526607..dc90c8efe08c 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -581,7 +581,7 @@ CONFIG_SPI_SH_MSIOF=m
 CONFIG_SPI_SUN6I=y
 CONFIG_SPI_TEGRA210_QUAD=m
 CONFIG_SPI_TEGRA114=m
-CONFIG_SPI_SPIDEV=m
+CONFIG_SPI_SPIDEV=y
 CONFIG_SPI_SLAVE=y
 CONFIG_SPMI=y
 CONFIG_PINCTRL_MAX77620=y

root@am62xx-evm:/home# ls -l /sys/bus/spi/devices/ -l
total 0
lrwxrwxrwx 1 root root 0 Apr 28  2022 spi0.0 -> ../../../devices/platform/bus@f0000/fc00000.bus/fc40000.spi/spi_master/spi0/spi0.0
lrwxrwxrwx 1 root root 0 Jan  1 00:02 spi1.1 -> ../../../devices/platform/bus@f0000/20100000.spi/spi_master/spi1/spi1.1
lrwxrwxrwx 1 root root 0 Jan  1 00:02 spi2.1 -> ../../../devices/platform/bus@f0000/20120000.spi/spi_master/spi2/spi2.1
root@am62xx-evm:/home#
root@am62xx-evm:/home# ./spidev_test -D /dev/spidev1.1 -s 7000000 -v -p '1234567'
spi mode: 0x0
bits per word: 8
max speed: 7000000 Hz (7000 kHz)
TX | 31 32 33 34 35 36 37 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __  |1234567|
RX | 00 00 00 00 00 00 00 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __  |.......|
root@am62xx-evm:/home#
root@am62xx-evm:/home#
root@am62xx-evm:/home# ./spidev_test -D /dev/spidev2.1 -s 7000000 -v -p '1234567'
spi mode: 0x0
bits per word: 8
max speed: 7000000 Hz (7000 kHz)
TX | 31 32 33 34 35 36 37 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __  |1234567|
RX | 00 00 00 00 00 00 00 __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __  |.......|

I see the following same output on running spidev_test application with both spi0 and spi2 utilizing CS1 in both cases:

Note that the extra gpio-hog for spi2 is used due to muxing of UART1 and SPI2 using FET switch controlled by i2c expander on TI EVM.

You may cross check this at your end with a TI EVM.

I can only think of 2 possible issues on your setup:
1. S/W issue: The pins you are configuring for SPI are also actively pinmuxed for some other IP (GPIO/ePWM/etc).
2. H/W issue: Something is affecting the direct SoC ball output on your board, either a switch or something else.