AM2431: How to Address SYSFW-6093

Hello Katsuyuki Sasjima-san,

Thank you for your query ! As it initially addresses our Sitara Processors hardware applications team but related to SYSFW, I need to internally discuss if it shall be re-assigned to the SITARA Software team. Please expect a response today or tomorrow.

Thanks

Best Regards

Anastas Yordanov 

Hello Anastas Yordanov,

How is the progress on this matter?

Best Regards
Katsuyuki Sasajima

Hello Anastas Yordanov,

Thank you for your response.

I would like to confirm two points.
- Regarding the past thread (e2e.ti.com/.../4947621)
specifically refers to what kind of issues caused by excessive jitter from the PLL output? I'd like to know if this occurs during CLK configuration or also during normal operation.
I want to understand what kind of impact this has on each controller.

・It states that applying the latest version is the only solution, but as explained earlier, updating the SDK to the latest version is difficult for us. Is it possible for us to manually configure the PLL settings ourselves by referring to the manual? Please confirm whether the information currently provided in the latest TRM is sufficient for this purpose.

Best Regards
Katsuyuki Sasajima

Hello Katsuyuki Sasajima-san,

Unfortunately, as already highlighted inside the linked thread:

AM6442: possible to set REF_DIV=other than 1(contenue) - Processors forum - Processors - TI E2E support forums

I got the confirmation from the same expert.

Please allow me some time to internally check on the possible impact and check on a last resort solution.

Please ping the thread if you don't get a response by mid of the next week.

Thanks

Best Regards

Anastas Yordanov

Hello Anastas Yordanov,

We greatly appreciate your consideration of a last resort solution.
How is the progress coming along since then?

Best Regards
Katsuyuki Sasajima

Hi Katsuyuki Sasajima-san,

Apologies for my delayed reply !  

I have discussed with my colleagues from the SITARA MPU Hardware Applications team as well:

Katsuyuki Sasajima said:

specifically refers to what kind of issues caused by excessive jitter from the PLL output? I'd like to know if this occurs during CLK configuration or also during normal operation.

Unfortunately, it will occur during normal operation too. A PLL synthesizer has a defined ref. input frequency range MIN-MAX of operating values. For the AM243x MAIN_PLL1 when the fref_clk input frequency is HFOSC freq.=25MHz / 5 = 5 MHz rather than 25MHz / 1 = 25MHz, it will be below the allowed minimal PLL_input_frequency, and there will be unacceptable jittering of the PLL output frequency to the PLL controllers over time. 

Katsuyuki Sasajima said:

I want to understand what kind of impact this has on each controller.

The frequency outputs at the MAIN_PLL1 controller HSDIV dividers will have unstable behavior. So this will cause erroneous behavior of the communication interfaces and subsystems, for the ones which are clock-supplied by the MAIN1 PLL controllers dividers. 

As you know the MAIN PLL1 input FREF_CLK divider is controlled in the SYSFW and according to the SDK team there is no workaround possible from custom software or in the SYSFW. A newer SDK > ver.10 SDK shall be installed and used to produce / re-flash the SYSFW + implemented errata for reliable AM62A7-Q1 system and interface operations.  

Please let me know if you have any additional questions.

Thanks for your understanding !

Best Regards

Anastas Yordanov

Hi Katsuyuki Sasajima-san,

I haven’t heard from you for about a couple of months, so I’m assuming you were able to resolve your issue. If this isn’t the case, please click the "This did NOT resolve my issue" button and reply to this thread with more information. If this thread locks, please click the "Ask a related question" button and in the new thread describe the current status of your issue and any additional details you may have to assist us in helping to solve your issues.

Regards,
Anastas Yordanov