Part Number: AM6442
Hi all,
I'm beating my head against trying to boot from the eMMC, and need some help trying to get it to transition to tispl.bin
I've successfully booted the tiboot3.bin, but it looks to be failing when trying to load the tispl.bin.
The eMMC used has 4MiB boot partitions rather than the 8MiB used on the evm(s), but the structure should be adjusted accordingly.
I've been able to get the custom board up to u-boot successfully via UART, flashed the eMMC from a usb drive, set the partconf and bootbus parameters (the warm-reset enable has been already done), read back sections from the eMMC into memory to verify the writes, powered off the unit, set the boot mode pins B6B5B4B3 to 1001, powered on, and the tiboot3.bin loads, but fails to transition to the tispl.bin.
uart log for load and boot:
=> usb reset
resetting USB...
Bus usb@f400000: Register 2000840 NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus usb@f400000 for devices... 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
=> mmc dev 0 1
switch to partitions #1, OK
mmc0(part 1) is current device
=> fatload usb 0 ${loadaddr} tiboot3.bin
495414 bytes read in 24 ms (19.7 MiB/s)
=> mmc write ${loadaddr} 0x0 0x400
MMC write: dev # 0, block # 0, count 1024 ... 1024 blocks written: OK
=> fatload usb 0 ${loadaddr} tispl.bin
1116999 bytes read in 50 ms (21.3 MiB/s)
=> mmc write ${loadaddr} 0x400 0xE00
MMC write: dev # 0, block # 1024, count 3584 ... 3584 blocks written: OK
=> fatload usb 0 ${loadaddr} u-boot.img
1430879 bytes read in 64 ms (21.3 MiB/s)
=> mmc write ${loadaddr} 0x1200 0xD00
MMC write: dev # 0, block # 4608, count 3328 ... 3328 blocks written: OK
=> mmc partconf 0 1 1 1
=> mmc bootbus 0 2 0 0
Set to BOOT_BUS_WIDTH = 0x2, RESET = 0x0, BOOT_MODE = 0x0
=>
U-Boot SPL 2025.01-g53c3fc94ae63-dirty (Feb 04 2026 - 12:26:49 +0100)
Resetting on cold boot to workaround ErrataID:i2331
Please resend tiboot3.bin in case of UART/DFU boot
resetting ...
U-Boot SPL 2025.01-g53c3fc94ae63-dirty (Feb 04 2026 - 12:26:49 +0100)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.1.2--v11.01.02 (Fancy Rat)')
Timed out in wait_for_event: status=0000
Check if pads/pull-ups of bus are properly configured
EEPROM not available at 0x50, trying to read at 0x51
Timed out in wait_for_event: status=0000
Check if pads/pull-ups of bus are properly configured
Reading on-board EEPROM at 0x51 failed -121
=== About to init DDR via UCLASS_RAM ===
=== DDR init returned success ===
=== Comprehensive DDR Test ===
@0x80000000: wrote 0xa5a50000, read 0xa5a50000 PASS
@0x81000000: wrote 0xa5a50001, read 0xa5a50001 PASS
@0x82000000: wrote 0xa5a50002, read 0xa5a50002 PASS
@0x84000000: wrote 0xa5a50003, read 0xa5a50003 PASS
@0x88000000: wrote 0xa5a50004, read 0xa5a50004 PASS
=== Walking bits test @0x82000000 ===
Walking bits PASS
=== Address uniqueness test ===
=== Cache coherency test ===
After cache activity: read 0xdeadbeef PASS
=== All DDR tests DONE ===
JGU get_boot_device: devstat = 0xcd4b bootmedia = 0x9 bootmode = 0
=== [1] spl_relocate_stack_gd: Entry ===
=== [2] CONFIG_SPL_STACK_R_ADDR = 0x82000000 ===
JGU: SPL initial stack usage: 13520 bytes
=== [3] After stack check ===
SPL malloc() before relocation used 0x1db4 bytes (7 KB)
=== [4] After malloc debug ===
=== [5] After malloc setup ===
=== Testing DDR at 0x81c00000 ===
=== DDR test: wrote 0xDEADBEEF, read 0xdeadbeef PASS ===
=== [6] new ptr = 0x81ffff30 ===
=== [7] About to memcpy ===
=== [8] After memcpy ===
=== [9] About to dm_fixup_for_gd_move ===
=== [DM1] dm_fixup_for_gd_move entry ===
=== [DM1a] gd=0x7011b730 new_gd=0x81ffff30 ===
=== [DM1b] gd->dm_root=0x7011b818 ===
=== [DM2] entered if: gd->dm_root exists ===
=== [DM2a] new_gd->uclass_root=0x7011b7dc ===
=== [DM2b] new_gd->uclass_root->next=0x7011d314 ===
=== [DM2c] About to write to next->prev ===
=== [DM3] after next->prev before prev->next ===
=== [DM3a] new_gd->uclass_root->prev=0x7011b810 ===
=== [DM3b] About to write to prev->next ===
=== [DM4] after prev->next ===
=== [DM5] dm_fixup_for_gd_move exit ===
=== [10] After dm_fixup_for_gd_move ===
=== BOARD_INIT_R called (call #1) sp= gd= ===
>>SPL: board_init_r()
spl_init
JGU get_boot_device: devstat = 0xcd4b bootmedia = 0x9 bootmode = 0
=== BOOT_FROM_DEVICES: count=5 ===
=== Trying bootdev[0]=0x9 ===
=== Found loader for 0x9 ===
Trying to boot from MMC1
Raw boot image support not enabled, proceeding to other boot methods
mmc_load_image_raw_sector: mmc block read error
Partition 1 invalid on device 0
spl_register_fat_device: fat register err - -1
spl_load_image_fat: error reading image tispl.bin, err - -1
=== BOOT FAILED from 0x9 ===
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ### verification of files from eMMC against binaries
> mmc dev 0 1
switch to partitions #1, OK
mmc0(part 1) is current device
=> mmc read 0x82000000 0x400 0x10
MMC read: dev # 0, block # 1024, count 16 ... 16 blocks read: OK
=> md 0x82000000
82000000: edfe0dd0 470b1100 38000000 f4061100 .......G...8....
82000010: 28000000 11000000 02000000 00000000 ...(............
82000020: 6d000000 bc061100 00000000 00000000 ...m............
82000030: 00000000 00000000 01000000 00000000 ................
82000040: 03000000 04000000 63000000 832d8369 ...........ci.-.
82000050: 03000000 04000000 54000000 01000000 ...........T....
82000060: 03000000 22000000 48000000 666e6f43 ......."...HConf
82000070: 72756769 6f697461 6f74206e 616f6c20 iguration to loa
82000080: 54412064 6e612046 50532064 0000004c d ATF and SPL...
82000090: 01000000 67616d69 00007365 01000000 ....images......
820000a0: 00667461 03000000 04000000 42000000 atf............B
820000b0: 00001c70 03000000 04000000 3d000000 p..............=
820000c0: 00001c70 03000000 15000000 3a000000 p..............:
820000d0: 2d6d7261 73757274 2d646574 6d726966 arm-trusted-firm
820000e0: 65726177 00000000 03000000 05000000 ware............
820000f0: 2e000000 656e6f6e 00000000 03000000 ....none........
=> mmc read 0x82000000 0x1200 0x10
MMC read: dev # 0, block # 4608, count 16 ... 16 blocks read: OK
=> md 0x82000000
82000000: edfe0dd0 5fd51500 38000000 3cd11500 ......._...8...<
82000010: 28000000 11000000 02000000 00000000 ...(............
82000020: 63000000 04d11500 00000000 00000000 ...c............
82000030: 00000000 00000000 01000000 00000000 ................
82000040: 03000000 04000000 53000000 832d8369 ...........Si.-.
82000050: 03000000 27000000 47000000 20544946 .......'...GFIT
82000060: 67616d69 69772065 6d206874 69746c75 image with multi
82000070: 20656c70 666e6f63 72756769 6f697461 ple configuratio
82000080: 0000736e 01000000 67616d69 00007365 ns......images..
82000090: 01000000 6f6f6275 00000074 03000000 ....uboot.......
820000a0: 04000000 42000000 00008080 03000000 .......B........
820000b0: 05000000 36000000 656e6f6e 00000000 .......6none....
820000c0: 03000000 04000000 31000000 006d7261 ...........1arm.
820000d0: 03000000 07000000 2e000000 6f622d75 ............u-bo
820000e0: 0000746f 03000000 09000000 29000000 ot.............)
820000f0: 6d726966 65726177 00000000 03000000 firmware........
=> mmc read 0x82000000 0x000 0x10
MMC read: dev # 0, block # 0, count 16 ... 16 blocks read: OK
=> md 0x82000000
82000000: f6078230 de058230 010203a0 27140202 0...0..........'
82000010: 58a1774b 2944a431 68ec10da afd6ba00 Kw.X1.D)...h....
82000020: 30e2e2fe 2a09060d f7864886 0d01010d ...0...*.H......
82000030: 81300005 300b319d 55030609 02130604 ..0..1.0...U....
82000040: 0b315355 03060930 0c080455 31585402 US1.0...U....TX1
82000050: 060d300f 07045503 6144060c 73616c6c .0...U....Dallas
82000060: 25302731 04550306 541e0c0a 73617865 1'0%..U....Texas
82000070: 736e4920 6d757274 73746e65 636e4920 Instruments Inc
82000080: 6f70726f 65746172 30133164 55030611 orporated1.0...U
82000090: 0a0c0b04 636f7250 6f737365 13317372 ....Processors1.
820000a0: 03061130 0c030455 2049540a 70707553 0...U....TI Supp
820000b0: 3174726f 061b301d 48862a09 010df786 ort1.0...*.H....
820000c0: 0e160109 70707573 4074726f 632e6974 ....support@ti.c
820000d0: 1e306d6f 36320d17 34303230 37323131 om0...2602041127
820000e0: 175a3135 3036320d 31363033 35373231 51Z..26030611275
820000f0: 81305a31 300b319d 55030609 02130604 1Z0..1.0...U....
=>
14:25:44:james@muu-dev:~/ti-processor-sdk-linux-am64xx-evm-11.01.05.03/board-support/ti-u-boot-2025.01+git/files_to_load$ xxd -l 0xF0 tispl.bin
00000000: d00d feed 0011 0b47 0000 0038 0011 06f4 .......G...8....
00000010: 0000 0028 0000 0011 0000 0002 0000 0000 ...(............
00000020: 0000 006d 0011 06bc 0000 0000 0000 0000 ...m............
00000030: 0000 0000 0000 0000 0000 0001 0000 0000 ................
00000040: 0000 0003 0000 0004 0000 0063 6983 2d83 ...........ci.-.
00000050: 0000 0003 0000 0004 0000 0054 0000 0001 ...........T....
00000060: 0000 0003 0000 0022 0000 0048 436f 6e66 ......."...HConf
00000070: 6967 7572 6174 696f 6e20 746f 206c 6f61 iguration to loa
00000080: 6420 4154 4620 616e 6420 5350 4c00 0000 d ATF and SPL...
00000090: 0000 0001 696d 6167 6573 0000 0000 0001 ....images......
000000a0: 6174 6600 0000 0003 0000 0004 0000 0042 atf............B
000000b0: 701c 0000 0000 0003 0000 0004 0000 003d p..............=
000000c0: 701c 0000 0000 0003 0000 0015 0000 003a p..............:
000000d0: 6172 6d2d 7472 7573 7465 642d 6669 726d arm-trusted-firm
000000e0: 7761 7265 0000 0000 0000 0003 0000 0005 ware............
14:28:23:james@muu-dev:~/ti-processor-sdk-linux-am64xx-evm-11.01.05.03/board-support/ti-u-boot-2025.01+git/files_to_load$ xxd -l 0xF0 u-boot.img
00000000: d00d feed 0015 d55f 0000 0038 0015 d13c ......._...8...<
00000010: 0000 0028 0000 0011 0000 0002 0000 0000 ...(............
00000020: 0000 0063 0015 d104 0000 0000 0000 0000 ...c............
00000030: 0000 0000 0000 0000 0000 0001 0000 0000 ................
00000040: 0000 0003 0000 0004 0000 0053 6983 2d83 ...........Si.-.
00000050: 0000 0003 0000 0027 0000 0047 4649 5420 .......'...GFIT
00000060: 696d 6167 6520 7769 7468 206d 756c 7469 image with multi
00000070: 706c 6520 636f 6e66 6967 7572 6174 696f ple configuratio
00000080: 6e73 0000 0000 0001 696d 6167 6573 0000 ns......images..
00000090: 0000 0001 7562 6f6f 7400 0000 0000 0003 ....uboot.......
000000a0: 0000 0004 0000 0042 8080 0000 0000 0003 .......B........
000000b0: 0000 0005 0000 0036 6e6f 6e65 0000 0000 .......6none....
000000c0: 0000 0003 0000 0004 0000 0031 6172 6d00 ...........1arm.
000000d0: 0000 0003 0000 0007 0000 002e 752d 626f ............u-bo
000000e0: 6f74 0000 0000 0003 0000 0009 0000 0029 ot.............)
14:28:39:james@muu-dev:~/ti-processor-sdk-linux-am64xx-evm-11.01.05.03/board-support/ti-u-boot-2025.01+git/files_to_load$ xxd -l 0xF0 tiboot3.bin
00000000: 3082 07f6 3082 05de a003 0201 0202 1427 0...0..........'
00000010: 4b77 a158 31a4 4429 da10 ec68 00ba d6af Kw.X1.D)...h....
00000020: fee2 e230 0d06 092a 8648 86f7 0d01 010d ...0...*.H......
00000030: 0500 3081 9d31 0b30 0906 0355 0406 1302 ..0..1.0...U....
00000040: 5553 310b 3009 0603 5504 080c 0254 5831 US1.0...U....TX1
00000050: 0f30 0d06 0355 0407 0c06 4461 6c6c 6173 .0...U....Dallas
00000060: 3127 3025 0603 5504 0a0c 1e54 6578 6173 1'0%..U....Texas
00000070: 2049 6e73 7472 756d 656e 7473 2049 6e63 Instruments Inc
00000080: 6f72 706f 7261 7465 6431 1330 1106 0355 orporated1.0...U
00000090: 040b 0c0a 5072 6f63 6573 736f 7273 3113 ....Processors1.
000000a0: 3011 0603 5504 030c 0a54 4920 5375 7070 0...U....TI Supp
000000b0: 6f72 7431 1d30 1b06 092a 8648 86f7 0d01 ort1.0...*.H....
000000c0: 0901 160e 7375 7070 6f72 7440 7469 2e63 ....support@ti.c
000000d0: 6f6d 301e 170d 3236 3032 3034 3131 3237 om0...2602041127
000000e0: 3531 5a17 0d32 3630 3330 3631 3132 3735 51Z..26030611275
the r5.config
CONFIG_TARGET_AM642_R5_MUU=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-muu"
CONFIG_OF_LIST="k3-am642-r5-muu"
CONFIG_SPL_OF_LIST="k3-am642-r5-muu"
CONFIG_SPL_MAX_SIZE=0x80000
CONFIG_SPL_PAD_TO=0x80000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
CONFIG_SPL_MMC_PREFER_EMMC_BOOT=y
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y
CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION=1
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_PHY_TI=y
CONFIG_PHY_TI_GENERIC=y
# CONFIG_PANIC_HANG is not set
#CONFIG_TARGET_AM625_R5_EVM is not set
#CONFIG_TI_I2C_BOARD_DETECT is not set
k3-am642-r5-muu.dts
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-am642-muu.dts"
#include "k3-am64-muu-lp4-1600MTs.dtsi"
#include "k3-am64-ddr.dtsi"
#include "k3-am642-muu-u-boot.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
clock-names = "gtc", "core";
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1000000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
clk_200mhz: dummy-clock-200mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
bootph-pre-ram;
};
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
mbox-names = "tx", "rx";
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&sdhci0 {
clocks = <&clk_200mhz>;
clock-names = "clk_xin";
};
&sdhci1 {
status = "disabled";
};
&serdes_wiz0 {
status = "okay";
};
/* UART is initialized before SYSFW is started
* so we can't do any power-domain/clock operations.
* Delete clock/power-domain properties to avoid
* UART init failure
*/
&main_uart0 {
/delete-property/ power-domains;
/delete-property/ clocks;
/delete-property/ clock-names;
};
/* timer init is called as part of rproc_start() while
* starting System Firmware, so any clock/power-domain
* operations will fail as SYSFW is not yet up and running.
* Delete all clock/power-domain properties to avoid
* timer init failure.
* This is an always on timer at 20MHz.
*/
&main_timer0 {
/delete-property/ clocks;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ power-domains;
};
&ospi0 {
reg = <0x00 0x0fc40000 0x00 0x100>,
<0x00 0x60000000 0x00 0x8000000>;
};
&memorycontroller {
ti,ddr-freq0 = <50000000>; /* 50MHz for F0 boot frequency */
};
k3-am642-muu.dts
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy.h>
#include "k3-am642.dtsi"
#include "k3-serdes.h"
/ {
compatible = "dripdrop,am642-muu", "dripdrop,am642";
model = "Dripdrop AM642 MUU";
chosen {
stdout-path = &main_uart0;
};
aliases {
serial0 = &mcu_uart0;
serial1 = &main_uart0;
i2c0 = &main_i2c0;
i2c1 = &main_i2c1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
ethernet0 = &cpsw_port1; /* CPSW RGMII1 (MDIO 0x9) */
ethernet1 = &cpsw_port2; /* CPSW RGMII2 (MDIO 0x11) */
ethernet2 = &icssg0_prueth_port0; /* ICSSG0 RGMII1 (MDIO 0x15) */
adc0 = &tscadc0;
};
memory@80000000 {
bootph-pre-ram;
device_type = "memory";
/* 1G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4000000 0x00 0x100000>;
no-map;
};
mcu_m4fss_memory_region: m4f-memory@a4100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a5000000 {
reg = <0x00 0xa5000000 0x00 0x00800000>;
alignment = <0x1000>;
no-map;
};
};
vusb_main: regulator-0 {
/* USB MAIN INPUT 5V DC */
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vusb_main5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
vcc_3v3_sys: regulator-1 {
/* output of LP8733xx */
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vcc_3v3_sys";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vusb_main>;
regulator-always-on;
regulator-boot-on;
};
/* 1.8V I/O rail for eMMC HS200/HS400 modes - from TPS6522053 pin 29 */
vcc_1v8_mmc: regulator-1v8-mmc {
bootph-all;
compatible = "regulator-fixed";
regulator-name = "vcc_1v8_mmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
/* Wi-Fi rail via board power switch — default ON; pull Y2 low to turn OFF */
wifi_vcc: regulator-wifi {
compatible = "regulator-fixed";
regulator-name = "wifi_vcc";
regulator-min-microvolt = <3300000>; /* set to your actual Wi-Fi rail */
regulator-max-microvolt = <3300000>;
/* Y2 → GPIO1_27; LOW disables power on your board */
gpio = <&main_gpio1 27 GPIO_ACTIVE_LOW>;
/* regulator-boot-on; // optional */
};
/* ===== Userspace GPIO exports (grouped) ===== */
gpio_export_power: gpio-export-power {
compatible = "gpio-export";
#size-cells = <0>;
ge_12v0_ext_en { gpios = <&main_gpio1 22 GPIO_ACTIVE_HIGH>; output; line-name = "12V0_EXT_EN"; };
ge_vpp_ldo_en { gpios = <&main_gpio1 32 GPIO_ACTIVE_HIGH>; output; line-name = "VPP_LDO_EN"; };
ge_reset_led { gpios = <&main_gpio1 60 GPIO_ACTIVE_LOW>; output; line-name = "RESET_LED_n"; };
ge_usb_pwr_fault { gpios = <&main_gpio1 33 GPIO_ACTIVE_HIGH>; line-name = "USB_PWR_FAULT_1V8"; };
ge_12v_out_status { gpios = <&main_gpio1 21 GPIO_ACTIVE_HIGH>; line-name = "12V_OUT_STATUS"; };
};
gpio_export_cell: gpio-export-cell {
compatible = "gpio-export";
#size-cells = <0>;
ge_cell_pwrkey { gpios = <&main_gpio1 36 GPIO_ACTIVE_LOW>; output; line-name = "CELL_PWRKEY_n"; };
ge_cell_resetkey { gpios = <&main_gpio1 35 GPIO_ACTIVE_LOW>; output; line-name = "CELL_RESETKEY_n"; };
ge_particle_pwr_en { gpios = <&main_gpio1 43 GPIO_ACTIVE_HIGH>; output; line-name = "PARTICLE_PWR_ENA"; };
ge_particle_mode { gpios = <&main_gpio1 17 GPIO_ACTIVE_HIGH>; line-name = "ParticleMODE_mpu"; };
ge_particle_reset { gpios = <&main_gpio1 18 GPIO_ACTIVE_LOW>; output; line-name = "ParticleRESET_mpu_n";};
ge_cell_status { gpios = <&main_gpio1 9 GPIO_ACTIVE_HIGH>; line-name = "CELL_MODEM_STATUS"; };
};
gpio_export_hub: gpio-export-hub {
compatible = "gpio-export";
#size-cells = <0>;
ge_hub_reset { gpios = <&main_gpio0 5 GPIO_ACTIVE_LOW>; output; line-name = "HUB_RESET_n"; };
ge_reset_pwr_solenoid { gpios = <&main_gpio0 2 GPIO_ACTIVE_LOW>; output; line-name = "RESET_PWR_SOLENOID_n"; };
ge_reset_pwr_cell { gpios = <&main_gpio0 3 GPIO_ACTIVE_LOW>; output; line-name = "RESET_PWR_CELL_n"; };
};
gpio_export_sim_endnote: gpio-export-sim-endnote {
compatible = "gpio-export";
#size-cells = <0>;
ge_sim_card_en { gpios = <&main_gpio1 44 GPIO_ACTIVE_HIGH>; output; line-name = "SIM_CARD_EN"; };
ge_sim_sel { gpios = <&main_gpio0 40 GPIO_ACTIVE_HIGH>; line-name = "SIM_SEL"; };
ge_endnote_on0 { gpios = <&main_gpio1 37 GPIO_ACTIVE_HIGH>; output; line-name = "ENDNOTE_ON.0"; };
ge_endnote_on1 { gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>; output; line-name = "ENDNOTE_ON.1"; };
ge_endnote_on2 { gpios = <&main_gpio0 33 GPIO_ACTIVE_HIGH>; output; line-name = "ENDNOTE_ON.2"; };
ge_endnote_on3 { gpios = <&main_gpio0 34 GPIO_ACTIVE_HIGH>; output; line-name = "ENDNOTE_ON.3"; };
ge_endnote_on4 { gpios = <&main_gpio0 35 GPIO_ACTIVE_HIGH>; output; line-name = "ENDNOTE_ON.4"; };
ge_endnote_on5 { gpios = <&main_gpio0 36 GPIO_ACTIVE_HIGH>; output; line-name = "ENDNOTE_ON.5"; };
ge_endnote_on6 { gpios = <&main_gpio0 37 GPIO_ACTIVE_HIGH>; output; line-name = "ENDNOTE_ON.6"; };
ge_endnote_on7 { gpios = <&main_gpio0 38 GPIO_ACTIVE_HIGH>; output; line-name = "ENDNOTE_ON.7"; };
};
/* ICSSG0 PRUETH single-EMAC on RGMII1 (port0) */
icssg0_prueth: icssg0-eth {
compatible = "ti,am642-icssg-prueth";
sram = <&oc_sram>;
pinctrl-names = "default";
pinctrl-0 = <&mypruicssg0rgmii1_pins_default>;
status = "disabled";
/* PRUSS cores */
ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>,
<&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
/* Firmware (ensure these exist under /lib/firmware/ti-pruss) */
firmware-name =
"ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
mii-g-rt = <&icssg0_mii_g_rt>;
mii-rt = <&icssg0_mii_rt>;
iep = <&icssg0_iep0>, <&icssg0_iep1>;
interrupt-parent = <&icssg0_intc>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
icssg0_prueth_port0: port@0 {
reg = <0>;
phy-mode = "rgmii-rxid";
phy-handle = <&icssg0_phy1>;
};
/* Keep port1 declared but unused */
port@1 {
reg = <1>;
fixed-link { speed = <100>; full-duplex; };
};
};
};
/* Optional helper: read HW_VER0 via hwmon (appears in /sys/class/hwmon/.../in4_input) */
iio_hwver: iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&tscadc0 4>; /* AIN4 index */
status = "okay";
};
};
/* ---- Pinmux blocks (auto-generated; edited only where noted) ---- */
/* Some or all of the pins from the following groups are not used by the device tree
lpddr4
emmc
usbsuper
*/
&main_pmx0 {
/* eMMC (MMC0) - dedicated pins on AM6442 */
main_mmc0_pins_default: main-mmc0-default-pins {
bootph-all;
pinctrl-single,pins = <
AM64X_IOPAD(0x01d8, PIN_INPUT, 0) /* (G18) MMC0_CLK */
AM64X_IOPAD(0x01d4, PIN_INPUT_PULLUP, 0) /* (J21) MMC0_CMD */
AM64X_IOPAD(0x01d0, PIN_INPUT_PULLUP, 0) /* (K20) MMC0_DAT0 */
AM64X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 0) /* (J20) MMC0_DAT1 */
AM64X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 0) /* (J18) MMC0_DAT2 */
AM64X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 0) /* (J17) MMC0_DAT3 */
AM64X_IOPAD(0x01c0, PIN_INPUT_PULLUP, 0) /* (H17) MMC0_DAT4 */
AM64X_IOPAD(0x01bc, PIN_INPUT_PULLUP, 0) /* (H19) MMC0_DAT5 */
AM64X_IOPAD(0x01b8, PIN_INPUT_PULLUP, 0) /* (H18) MMC0_DAT6 */
AM64X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (G17) MMC0_DAT7 */
AM64X_IOPAD(0x01dc, PIN_INPUT_PULLDOWN, 0) /* (G19) MMC0_DS */
>;
};
myadc1_pins_default: myadc1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x02c0, PIN_INPUT, 0) /* (G21) ADC0_AIN4 */
AM64X_IOPAD(0x02c4, PIN_INPUT, 0) /* (F21) ADC0_AIN5 */
>;
};
/* CPSW RGMII1/2 combined group */
mycpsw1_pins_default: mycpsw1-default-pins {
bootph-all;
pinctrl-single,pins = <
AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
>;
};
io_3V3_pins_default: io-3v3-default-pins {
bootph-all;
pinctrl-single,pins = <
AM64X_IOPAD(0x0000, PIN_INPUT_PULLUP, 7) /* (N20) OSPI0_CLK.GPIO0_0 */
AM64X_IOPAD(0x0004, PIN_OUTPUT_PULLUP, 7) /* (N21) OSPI0_LBCLKO.GPIO0_1 */
AM64X_IOPAD(0x0008, PIN_OUTPUT_PULLDOWN, 7) /* (N19) OSPI0_DQS.GPIO0_2 */
AM64X_IOPAD(0x000c, PIN_OUTPUT_PULLDOWN, 7) /* (M19) OSPI0_D0.GPIO0_3 */
AM64X_IOPAD(0x0014, PIN_OUTPUT_PULLUP, 7) /* (M20) OSPI0_D2.GPIO0_5 */
AM64X_IOPAD(0x001c, PIN_OUTPUT_PULLUP, 7) /* (P21) OSPI0_D4.GPIO0_7 */
AM64X_IOPAD(0x0020, PIN_OUTPUT_PULLUP, 7) /* (P20) OSPI0_D5.GPIO0_8 */
AM64X_IOPAD(0x0024, PIN_OUTPUT_PULLUP, 7) /* (N18) OSPI0_D6.GPIO0_9 */
AM64X_IOPAD(0x0034, PIN_OUTPUT_PULLDOWN, 7) /* (K17) OSPI0_CSn2.GPIO0_13 */
AM64X_IOPAD(0x0038, PIN_OUTPUT_PULLDOWN, 7) /* (L17) OSPI0_CSn3.GPIO0_14 */
AM64X_IOPAD(0x003c, PIN_INPUT, 7) /* (T20) GPMC0_AD0.GPIO0_15 */
AM64X_IOPAD(0x0040, PIN_INPUT, 7) /* (U21) GPMC0_AD1.GPIO0_16 */
AM64X_IOPAD(0x0044, PIN_INPUT, 7) /* (T18) GPMC0_AD2.GPIO0_17 */
AM64X_IOPAD(0x0048, PIN_INPUT, 7) /* (U20) GPMC0_AD3.GPIO0_18 */
AM64X_IOPAD(0x0054, PIN_INPUT, 7) /* (V20) GPMC0_AD6.GPIO0_21 */
AM64X_IOPAD(0x0058, PIN_INPUT, 7) /* (V21) GPMC0_AD7.GPIO0_22 */
AM64X_IOPAD(0x005c, PIN_INPUT, 7) /* (V19) GPMC0_AD8.GPIO0_23 */
AM64X_IOPAD(0x0060, PIN_INPUT, 7) /* (T17) GPMC0_AD9.GPIO0_24 */
AM64X_IOPAD(0x0064, PIN_INPUT, 7) /* (R16) GPMC0_AD10.GPIO0_25 */
AM64X_IOPAD(0x0068, PIN_INPUT, 7) /* (W20) GPMC0_AD11.GPIO0_26 */
AM64X_IOPAD(0x006c, PIN_INPUT, 7) /* (W21) GPMC0_AD12.GPIO0_27 */
AM64X_IOPAD(0x0070, PIN_INPUT, 7) /* (V18) GPMC0_AD13.GPIO0_28 */
AM64X_IOPAD(0x0074, PIN_INPUT, 7) /* (Y21) GPMC0_AD14.GPIO0_29 */
AM64X_IOPAD(0x0078, PIN_INPUT, 7) /* (Y20) GPMC0_AD15.GPIO0_30 */
AM64X_IOPAD(0x007c, PIN_OUTPUT_PULLUP, 7) /* (R17) GPMC0_CLK.GPIO0_31 */
AM64X_IOPAD(0x0084, PIN_OUTPUT_PULLUP, 7) /* (P16) GPMC0_ADVn_ALE.GPIO0_32 */
AM64X_IOPAD(0x0088, PIN_OUTPUT_PULLUP, 7) /* (R18) GPMC0_OEn_REn.GPIO0_33 */
AM64X_IOPAD(0x008c, PIN_OUTPUT_PULLUP, 7) /* (T21) GPMC0_WEn.GPIO0_34 */
AM64X_IOPAD(0x0090, PIN_OUTPUT_PULLUP, 7) /* (P17) GPMC0_BE0n_CLE.GPIO0_35 */
AM64X_IOPAD(0x0094, PIN_OUTPUT_PULLUP, 7) /* (T19) GPMC0_BE1n.GPIO0_36 */
AM64X_IOPAD(0x0098, PIN_OUTPUT_PULLUP, 7) /* (W19) GPMC0_WAIT0.GPIO0_37 */
AM64X_IOPAD(0x009c, PIN_OUTPUT_PULLUP, 7) /* (Y18) GPMC0_WAIT1.GPIO0_38 */
AM64X_IOPAD(0x00a0, PIN_INPUT_PULLUP, 7) /* (N16) GPMC0_WPn.GPIO0_39 */
AM64X_IOPAD(0x00a4, PIN_INPUT_PULLUP, 7) /* (N17) GPMC0_DIR.GPIO0_40 */
AM64X_IOPAD(0x00ac, PIN_INPUT_PULLDOWN, 7) /* (R20) GPMC0_CSn1.GPIO0_42 */
AM64X_IOPAD(0x00b4, PIN_OUTPUT_PULLUP, 7) /* (R21) GPMC0_CSn3.GPIO0_44 */
AM64X_IOPAD(0x004c, PIN_INPUT, 7) /* (U18) GPMC0_AD4.GPIO0_82 */
AM64X_IOPAD(0x0050, PIN_INPUT, 7) /* (U19) GPMC0_AD5.GPIO0_83 */
>;
};
former1v8ionow3v3_pins_default: former1v8ionow3v3-default-pins {
bootph-all;
pinctrl-single,pins = <
AM64X_IOPAD(0x017c, PIN_OUTPUT_PULLUP, 7) /* (T1) PRG0_PRU0_GPO7.GPIO1_7 */
AM64X_IOPAD(0x0184, PIN_INPUT_PULLUP, 7) /* (W6) PRG0_PRU0_GPO9.GPIO1_9 */
AM64X_IOPAD(0x01a4, PIN_OUTPUT_PULLUP, 7) /* (U1) PRG0_PRU0_GPO17.GPIO1_17 */
AM64X_IOPAD(0x01a8, PIN_OUTPUT_PULLUP, 7) /* (V1) PRG0_PRU0_GPO18.GPIO1_18 */
AM64X_IOPAD(0x01ac, PIN_INPUT_PULLDOWN, 7) /* (W1) PRG0_PRU0_GPO19.GPIO1_19 */
AM64X_IOPAD(0x01b0, PIN_OUTPUT_PULLDOWN, 7) /* (Y2) PRG0_PRU1_GPO0.GPIO1_20 */
AM64X_IOPAD(0x01b4, PIN_OUTPUT_PULLUP, 7) /* (W2) PRG0_PRU1_GPO1.GPIO1_21 */
AM64X_IOPAD(0x01b8, PIN_INPUT_PULLUP, 7) /* (V3) PRG0_PRU1_GPO2.GPIO1_22 */
AM64X_IOPAD(0x021c, PIN_OUTPUT_PULLUP, 7) /* (B14) SPI1_CS0.GPIO1_47 */
AM64X_IOPAD(0x0228, PIN_OUTPUT_PULLUP, 7) /* (B15) SPI1_D0.GPIO1_50 */
AM64X_IOPAD(0x0250, PIN_OUTPUT_PULLUP, 7) /* (A17) MCAN0_TX.GPIO1_60 */
AM64X_IOPAD(0x0270, PIN_OUTPUT, 7) /* (D18) ECAP0_IN_APWM_OUT.GPIO1_68 */
AM64X_IOPAD(0x0298, PIN_OUTPUT_PULLUP, 7) /* (D19) MMC1_SDCD.GPIO1_77 */
AM64X_IOPAD(0x029c, PIN_OUTPUT_PULLUP, 7) /* (C20) MMC1_SDWP.GPIO1_78 */
AM64X_IOPAD(0x02b0, PIN_INPUT, 7) /* (G20) ADC0_AIN0.GPIO1_80 */
>;
};
myi2c1_pins_default: myi2c1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x026c, PIN_INPUT, 0) /* (B19) I2C1_SDA */
>;
};
myi2c0_pins_default: myi2c0-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */
AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */
>;
};
/* CPSW MDIO */
mymdio1_pins_default: mymdio1-default-pins {
bootph-all;
pinctrl-single,pins = <
AM64X_IOPAD(0x015c, PIN_OUTPUT, 4) /* (Y6) PRG1_MDIO0_MDC.MDIO0_MDC */
AM64X_IOPAD(0x0158, PIN_INPUT, 4) /* (AA6) PRG1_MDIO0_MDIO.MDIO0_MDIO */
>;
};
wifisdio_pins_default: wifisdio-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x028c, PIN_OUTPUT, 0) /* (L20) MMC1_CLK */
AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
>;
};
/* ICSSG0 MDIO */
mypruicssg0mdio1_pins_default: mypruicssg0mdio1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0204, PIN_OUTPUT, 0) /* (P3) PRG0_MDIO0_MDC */
AM64X_IOPAD(0x0200, PIN_INPUT, 0) /* (P2) PRG0_MDIO0_MDIO */
>;
};
/* ICSSG0 RGMII1 */
mypruicssg0rgmii1_pins_default: mypruicssg0rgmii1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0160, PIN_INPUT, 2) /* (Y1) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
AM64X_IOPAD(0x0164, PIN_INPUT, 2) /* (R4) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
AM64X_IOPAD(0x0168, PIN_INPUT, 2) /* (U2) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
AM64X_IOPAD(0x016c, PIN_INPUT, 2) /* (V2) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
AM64X_IOPAD(0x0178, PIN_INPUT, 2) /* (T3) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
AM64X_IOPAD(0x0170, PIN_INPUT, 2) /* (AA2) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
AM64X_IOPAD(0x018c, PIN_OUTPUT, 2) /* (Y3) PRG0_PRU0_GPO11.PRG0_RGMII1_TD0 */
AM64X_IOPAD(0x0190, PIN_OUTPUT, 2) /* (AA3) PRG0_PRU0_GPO12.PRG0_RGMII1_TD1 */
AM64X_IOPAD(0x0194, PIN_OUTPUT, 2) /* (R6) PRG0_PRU0_GPO13.PRG0_RGMII1_TD2 */
AM64X_IOPAD(0x0198, PIN_OUTPUT, 2) /* (V4) PRG0_PRU0_GPO14.PRG0_RGMII1_TD3 */
AM64X_IOPAD(0x01a0, PIN_INPUT, 2) /* (U4) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
AM64X_IOPAD(0x019c, PIN_OUTPUT, 2) /* (T5) PRG0_PRU0_GPO15.PRG0_RGMII1_TX_CTL */
>;
};
myspi1_pins_default: myspi1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
AM64X_IOPAD(0x020c, PIN_OUTPUT, 0) /* (C13) SPI0_CS1 */
>;
};
mysystem1_pins_default: mysystem1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0274, PIN_INPUT_PULLUP, 0) /* (A19) EXT_REFCLK1 */
AM64X_IOPAD(0x025c, PIN_OUTPUT, 3) /* (D17) MCAN1_RX.OBSCLK0 */
AM64X_IOPAD(0x02ac, PIN_OUTPUT, 0) /* (E17) PORz_OUT */
AM64X_IOPAD(0x02a0, PIN_INPUT_PULLUP, 0) /* (E18) RESET_REQz */
AM64X_IOPAD(0x02a4, PIN_OUTPUT, 0) /* (F16) RESETSTATz */
>;
};
myuart1_pins_default: myuart1-default-pins {
bootph-all;
pinctrl-single,pins = <
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
>;
};
usbsuper_pins_default: usbsuper-default-pins {
bootph-all;
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
};
&mcu_pmx0 {
myjtag1_pins_default: myjtag1-default-pins {
pinctrl-single,pins = <
AM64X_MCU_IOPAD(0x007c, PIN_INPUT_PULLUP, 0) /* (D10) EMU0 */
AM64X_MCU_IOPAD(0x0080, PIN_INPUT_PULLUP, 0) /* (E10) EMU1 */
AM64X_MCU_IOPAD(0x0068, PIN_INPUT_PULLUP, 0) /* (B11) TCK */
AM64X_MCU_IOPAD(0x0070, PIN_INPUT_PULLUP, 0) /* (C11) TDI */
AM64X_MCU_IOPAD(0x0074, PIN_OUTPUT_PULLUP, 0) /* (A12) TDO */
AM64X_MCU_IOPAD(0x0078, PIN_INPUT_PULLUP, 0) /* (C12) TMS */
AM64X_MCU_IOPAD(0x006c, PIN_INPUT_PULLDOWN, 0) /* (D11) TRSTn */
>;
};
mymcuuart1_pins_default: mymcuuart1-default-pins {
pinctrl-single,pins = <
AM64X_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (C9) MCU_UART1_RXD */
AM64X_MCU_IOPAD(0x003c, PIN_OUTPUT, 0) /* (D9) MCU_UART1_TXD */
AM64X_MCU_IOPAD(0x0040, PIN_INPUT, 0) /* (B8) MCU_UART1_CTSn */
AM64X_MCU_IOPAD(0x0044, PIN_OUTPUT, 0) /* (B9) MCU_UART1_RTSn */
>;
};
mymcuuart2_pins_default: mymcuuart2-default-pins {
pinctrl-single,pins = <
AM64X_MCU_IOPAD(0x0030, PIN_INPUT, 0) /* (D8) MCU_UART0_CTSn */
AM64X_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (E8) MCU_UART0_RTSn */
AM64X_MCU_IOPAD(0x0028, PIN_INPUT, 0) /* (A9) MCU_UART0_RXD */
AM64X_MCU_IOPAD(0x002c, PIN_OUTPUT, 0) /* (A8) MCU_UART0_TXD */
>;
};
};
&fss { bootph-all; };
&main_uart0 {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&myuart1_pins_default>;
current-speed = <115200>;
};
&main_i2c0 {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&myi2c0_pins_default>;
clock-frequency = <400000>;
/* 0x50 — 24C512 EEPROM (AT24C512C-SSHM-T) */
eeprom@50 {
compatible = "atmel,24c512", "atmel,24c02";
reg = <0x50>;
pagesize = <128>;
};
/* 0x69 — RTC (AB1805) */
rtc@69 {
compatible = "abracon,ab1805";
reg = <0x69>;
/* Optional: set 32k/clkout, trickle, or wake gpios here if used */
};
/* 0x48 — Temp sensor (TMP100 on LPDDR4 area) */
temp-mem@48 {
compatible = "ti,tmp100";
reg = <0x48>;
};
/* 0x4a — Temp sensor (TMP100 on MPU) */
temp-mpu@4a {
compatible = "ti,tmp100";
reg = <0x4a>;
};
/* 0x30 — PMIC (TPS6522053) — verify binding */
pmic@30 {
compatible = "ti,tps65220";
reg = <0x30>;
};
};
&main_i2c1 {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&myi2c1_pins_default>;
clock-frequency = <400000>;
/* 0x60 — LED driver (TLC59116FIRHBR) */
leds@60 {
compatible = "nxp,tlc59116";
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
/* Optional: mode/current config; tweak for your board */
nxp,oe-sink = <1>; /* open-drain sink outputs */
/* nxp,brightness-max = <255>; */
/* OUT0..OUT14 map */
led@0 { reg = <0>; label = "POWER_LED"; };
led@1 { reg = <1>; label = "READY_LED"; };
led@2 { reg = <2>; label = "FAULT_LED"; };
led@3 { reg = <3>; label = "WAN_G"; };
led@4 { reg = <4>; label = "WAN_R"; };
led@5 { reg = <5>; label = "WAN_B"; };
led@6 { reg = <6>; label = "WIFI_G"; };
led@7 { reg = <7>; label = "WIFI_R"; };
led@8 { reg = <8>; label = "WIFI_B"; };
led@9 { reg = <9>; label = "CELL_G"; };
led@10 { reg = <10>; label = "CELL_R"; };
led@11 { reg = <11>; label = "CELL_B"; };
led@12 { reg = <12>; label = "SIGSTR_LED2"; };
led@13 { reg = <13>; label = "SIGSTR_LED1"; };
led@14 { reg = <14>; label = "SIGSTR_LED0"; };
/* OUT15 unused; add if you wire it later */
};
};
/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
&mcu_gpio0 { status = "reserved"; };
&mcu_gpio_intr { status = "reserved"; };
/* ===== GPIO hogs (controllers are defined in k3-am642.dtsi) ===== */
&main_gpio1 {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&former1v8ionow3v3_pins_default>;
/* System power / status */
pwr12v0_ext_en_hog: 12v0-ext-en-hog { gpio-hog; gpios = <22 GPIO_ACTIVE_HIGH>; output-high; line-name = "12V0_EXT_EN"; };
vpp_ldo_en_hog: vpp-ldo-en-hog { gpio-hog; gpios = <32 GPIO_ACTIVE_HIGH>; output-high; line-name = "VPP_LDO_EN"; };
usb_pwr_fault_hog: usb-pwr-fault-hog { gpio-hog; gpios = <33 GPIO_ACTIVE_HIGH>; input; line-name = "USB_PWR_FAULT_1V8"; };
stat12v_out_hog: 12v-out-status-hog { gpio-hog; gpios = <21 GPIO_ACTIVE_HIGH>; input; line-name = "12V_OUT_STATUS"; };
reset_led_hog: reset-led-hog { gpio-hog; gpios = <60 GPIO_ACTIVE_LOW>; output-high; line-name = "RESET_LED_n"; };
/* Cellular / Particle */
cell_pwrkey_hog: cell-pwrkey-hog { gpio-hog; gpios = <36 GPIO_ACTIVE_LOW>; output-high; line-name = "CELL_PWRKEY_n"; };
cell_resetkey_hog: cell-resetkey-hog { gpio-hog; gpios = <35 GPIO_ACTIVE_LOW>; output-high; line-name = "CELL_RESETKEY_n"; };
particle_pwr_ena_hog: particle-pwr-ena-hog { gpio-hog; gpios = <43 GPIO_ACTIVE_HIGH>; output-low; line-name = "PARTICLE_PWR_ENA"; };
particle_mode_hog: particle-mode-hog { gpio-hog; gpios = <17 GPIO_ACTIVE_HIGH>; input; line-name = "ParticleMODE_mpu"; };
particle_reset_hog: particle-reset-hog { gpio-hog; gpios = <18 GPIO_ACTIVE_LOW>; output-high; line-name = "ParticleRESET_mpu_n"; };
cell_modem_status_hog: cell-modem-status-hog { gpio-hog; gpios = <9 GPIO_ACTIVE_HIGH>; input; line-name = "CELL_MODEM_STATUS"; };
/* SIM enable (keep off at boot) */
sim_card_en_hog: sim-card-en-hog { gpio-hog; gpios = <44 GPIO_ACTIVE_HIGH>; output-low; line-name = "SIM_CARD_EN"; };
/* Endnote 0 */
endnote_on0_hog: endnote-on0-hog { gpio-hog; gpios = <37 GPIO_ACTIVE_HIGH>; output-low; line-name = "ENDNOTE_ON.0"; };
};
&main_gpio0 {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&io_3V3_pins_default>;
/* Hub / peripheral resets */
hub_reset_hog: hub-reset-hog { gpio-hog; gpios = <5 GPIO_ACTIVE_LOW>; output-high; line-name = "HUB_RESET_n"; };
reset_pwr_solenoid_hog: reset-pwr-solenoid-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_LOW>; output-high; line-name = "RESET_PWR_SOLENOID_n"; };
reset_pwr_cell_hog: reset-pwr-cell-hog { gpio-hog; gpios = <3 GPIO_ACTIVE_LOW>; output-high; line-name = "RESET_PWR_CELL_n"; };
/* SIM select (input unless you force a slot) */
sim_sel_hog: sim-sel-hog { gpio-hog; gpios = <40 GPIO_ACTIVE_HIGH>; input; line-name = "SIM_SEL"; };
/* Endnote 1..7 (default OFF) */
endnote_on1_hog: endnote-on1-hog { gpio-hog; gpios = <32 GPIO_ACTIVE_HIGH>; output-low; line-name = "ENDNOTE_ON.1"; };
endnote_on2_hog: endnote-on2-hog { gpio-hog; gpios = <33 GPIO_ACTIVE_HIGH>; output-low; line-name = "ENDNOTE_ON.2"; };
endnote_on3_hog: endnote-on3-hog { gpio-hog; gpios = <34 GPIO_ACTIVE_HIGH>; output-low; line-name = "ENDNOTE_ON.3"; };
endnote_on4_hog: endnote-on4-hog { gpio-hog; gpios = <35 GPIO_ACTIVE_HIGH>; output-low; line-name = "ENDNOTE_ON.4"; };
endnote_on5_hog: endnote-on5-hog { gpio-hog; gpios = <36 GPIO_ACTIVE_HIGH>; output-low; line-name = "ENDNOTE_ON.5"; };
endnote_on6_hog: endnote-on6-hog { gpio-hog; gpios = <37 GPIO_ACTIVE_HIGH>; output-low; line-name = "ENDNOTE_ON.6"; };
endnote_on7_hog: endnote-on7-hog { gpio-hog; gpios = <38 GPIO_ACTIVE_HIGH>; output-low; line-name = "ENDNOTE_ON.7"; };
};
/* Wi-Fi over SDIO (MMC1) */
&sdhci1 {
/* bootph-all;*/
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wifisdio_pins_default>; /* DAT0..3/CMD/CLK */
/* Slot power switch (keep if it powers SDIO domain/level shifters) */
/* vmmc-supply = <&wifi_vcc>; */
disable-wp;
#address-cells = <1>;
#size-cells = <0>;
/* WL1801 / WL18xx = SDIO function #2 */
wlcore: wlcore@2 {
compatible = "ti,wl1835"; /* valid for WL1801 */
reg = <2>;
/* ASIC power rail via the board switch */
vmmc-supply = <&wifi_vcc>;
/* IRQ on W1 → GPIO1_19 */
interrupt-parent = <&main_gpio1>;
interrupts = <19 IRQ_TYPE_EDGE_RISING>;
/* If your IRQ is active-low, switch to: IRQ_TYPE_EDGE_FALLING */
};
};
/* eMMC on MMC0 with reset (GPIO1_77 = D19).
*/
/* trying to simplify */
&sdhci0 {
status = "okay";
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
bootph-all;
};
&serdes_ln_ctrl { bootph-all; idle-states = <AM64_SERDES0_LANE0_USB>; };
&serdes_refclk { bootph-all; };
&serdes_wiz0 { bootph-all; };
&serdes0 {
bootph-all;
serdes0_usb_link: phy@0 {
bootph-all;
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_USB3>;
resets = <&serdes_wiz0 1>;
};
};
&usbss0 { bootph-all; ti,vbus-divider; };
&usb0 {
bootph-all;
dr_mode = "host";
maximum-speed = "super-speed";
pinctrl-names = "default";
pinctrl-0 = <&usbsuper_pins_default>;
phys = <&serdes0_usb_link>;
phy-names = "cdns3,usb3-phy";
};
/* ---------- ETHERNET (CPSW + ICSSG0) ---------- */
/* CPSW core */
&cpsw3g {
bootph-all;
pinctrl-names = "default";
pinctrl-0 = <&mycpsw1_pins_default>; /* use the defined group */
/* Map HW8_TS_PUSH to GENF1 */
cpts@3d000 { ti,pps = <7 1>; };
};
/* CPSW ports: RGMII with PHY-provided RX delay only */
&cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy11>; };
&cpsw_port2 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy9>; };
/* CPSW MDIO + DP83822 PHYs (with resets and IRQs) */
&cpsw3g_mdio {
bootph-all;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mymdio1_pins_default>;
/* MDIO address 11 (RGMII1) — reset on P20 -> GPIO0_6 */
cpsw3g_phy9: ethernet-phy@9 {
reg = <0x09>;
/* compatible = "ti,dp83822,ethernet-phy-ieee802.3-c22"; */
rx-internal-delay-ps = <1>; /* enable RX delay (fixed by driver) */
reset-gpios = <&main_gpio0 8 GPIO_ACTIVE_LOW>; /* P20 RESET_PHY_0 */
interrupt-parent = <&main_gpio1>;
interrupts = <39 IRQ_TYPE_LEVEL_LOW>; /* N16 INT_PWDN_N.0 */
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
};
/* MDIO address 9 (RGMII2) — reset on N18 -> GPIO0_7 */
cpsw3g_phy11: ethernet-phy@11 {
reg = <0x11>;
/* compatible = "ti,dp83822,ethernet-phy-ieee802.3-c22"; */
rx-internal-delay-ps = <1>; /* enable RX delay */
reset-gpios = <&main_gpio0 9 GPIO_ACTIVE_LOW>; /* N18 RESET_PHY_1 */
interrupt-parent = <&main_gpio1>;
interrupts = <40 IRQ_TYPE_LEVEL_LOW>; /* N17 INT_PWDN_N.1 */
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
};
};
/* ICSSG0 MDIO + DP83822 PHY @ (0x15) with reset on B14 -> GPIO1_47 */
&icssg0_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mypruicssg0mdio1_pins_default>;
icssg0_phy1: ethernet-phy@15 {
reg = <0x15>; /* 15 */
compatible = "ti,dp83822,ethernet-phy-ieee802.3-c22";
rx-internal-delay-ps = <1>; /* enable RX delay */
reset-gpios = <&main_gpio1 47 GPIO_ACTIVE_LOW>; /* B14 RESET_PHY_4 */
interrupt-parent = <&main_gpio1>;
interrupts = <50 IRQ_TYPE_LEVEL_LOW>; /* B15 INT_PWDN_N.4 */
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
};
};
/* Make sure ADC0 is enabled and pins are set */
&tscadc0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&myadc1_pins_default>; /* includes ADC0_AIN4 (G21) */
#io-channel-cells = <1>;
};
/* ---------- Mailboxes / R5F / M4F (unchanged) ---------- */
&mailbox0_cluster2 {
status = "okay";
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster4 {
status = "okay";
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster6 {
status = "okay";
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&mcu_m4fss {
mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
memory-region = <&mcu_m4fss_dma_memory_region>,
<&mcu_m4fss_memory_region>;
status = "okay";
};
/*
&ecap0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_ecap0_pins_default>;
};
&eqep0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_eqep0_pins_default>;
};
*/
/* TimeSync Router (unchanged except pinmux blocks already present) */
#define TS_OFFSET(pa, val) (0x4+(pa)*4) (0x10000 | val)
×ync_router {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&cpsw_cpts_pps>;
cpsw_cpts_pps: cpsw-cpts-pps {
pinctrl-single,pins = <
/* pps [cpts genf1] in22 -> out37 [cpts hw8_push] */
TS_OFFSET(37, 22)
/* pps [cpts genf1] in22 -> out26 [SYNC1_OUT pin] */
TS_OFFSET(26, 22)
>;
};
};
am64x_evm_r5_defconfig
CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SOC_K3_AM642=y
CONFIG_TARGET_AM642_R5_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7019b800
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-evm"
CONFIG_SPL_PCI_ENDPOINT=y
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL_TEXT_BASE=0x70000000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x7019b800
CONFIG_SPL_BSS_MAX_SIZE=0x4000
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x400000
CONFIG_SPL_SIZE_LIMIT=0x190000
CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
CONFIG_SPL_MAX_SIZE=0x180000
CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH=y
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NET=y
CONFIG_SPL_NET_VCI_STRING="AM64X U-Boot R5 SPL"
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_PCI_DFU=y
CONFIG_PCI_DFU_SPL_LOAD_FIT_ADDRESS=0x80800000
CONFIG_PCI_DFU_BAR_SIZE=0x400000
CONFIG_PCI_DFU_VENDOR_ID=0x104c
CONFIG_PCI_DFU_DEVICE_ID=0xb010
CONFIG_PCI_DFU_BOOT_PHASE="tiboot3.bin"
CONFIG_SPL_REMOTEPROC=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_SPL_THERMAL=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_OF_LIST="k3-am642-r5-evm k3-am642-r5-sk"
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SPL_CLK_CCF=y
CONFIG_CLK_CCF=y
CONFIG_CLK_TI_SCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_ESM_K3=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_S28HX_T=y
CONFIG_SPI_FLASH_MT35XU=y
CONFIG_PHY_TI_DP83867=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_PCIE_CDNS_TI_EP=y
CONFIG_PHY=y
CONFIG_SPL_PHY=y
CONFIG_PHY_CADENCE_SIERRA=y
CONFIG_PHY_CADENCE_TORRENT=y
CONFIG_PHY_J721E_WIZ=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_GENERIC is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_TI_K3_ARM64=y
CONFIG_RESET_TI_SCI=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y
CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_CADENCE_QSPI_PHY=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_DM_THERMAL=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_SPL_USB_HOST=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_CDNS3=y
CONFIG_USB_CDNS3_GADGET=y
CONFIG_USB_CDNS3_HOST=y
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_SPL_USB_CDNS3_HOST=y
CONFIG_USB_STORAGE=y
CONFIG_SPL_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_DFU=y
CONFIG_SPL_MTD=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
#changes made for debug
#CONFIG_SPL_SKIP_RELOCATE=y
#CONFIG_LOG=y
#CONFIG_LOG_MAX_LEVEL=7
#CONFIG_DM_DEBUG=y
#CONFIG_DM_WARN=y
# (some branches use CONFIG_DM_DEBUG_LOGLEVEL)
#CONFIG_DM_DEBUG_LEVEL=4
# LOGL_WARNING or LOGL_INFO
structure for partition
+------------------------------------+0x0 (sector 0x0000) +-------------------------+0x0
| tiboot3.bin (512 KB) | | |
+------------------------------------+0x80000 (sector 0x0400) | |
| tispl.bin (1.75 MB) | | rootfs |
+------------------------------------+0x240000 (sector 0x1200) | |
| u-boot.img (1.625 MB) | | |
+------------------------------------+0x3E0000 (sector 0x1F00) | |
| environment (16 KB) | | |
+------------------------------------+0x3E4000 (sector 0x1F20) | |
| backup environment (16 KB) | | |
+------------------------------------+0x3E8000 (sector 0x1F40) | |
| free (96 KB) | | |
+------------------------------------+0x400000 (sector 0x2000) +-------------------------+
Boot0 (4 MiB) UDA