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AM62L: AM62L: DDR memtester failed

Part Number: AM62L
Other Parts Discussed in Thread: SYSCONFIG

Hi TI

We are using AM62L devices with ti-processor-sdk-linux-rt-am62lxx-evm-11.01.16.13.

Currently, we are encountering errors during DDR memtester stress testing with TGDR4004JA and TGDR4008JA DDR4 memory.

 

The error message is as follows, it works normally when set to "memtester 128K 1":

root@AM62Lx:~# memtester 512K 1
memtester version 4.6.0 (64-bit)
Copyright (C) 2001-2020 Charles Cazabon.
Licensed under the GNU General Public License version 2 (only).

pagesize is 4096
pagesizemask is 0xfffffffffffff000
want 0MB (524288 bytes)
got  0MB (524288 bytes), trying mlock ...locked.
Loop 1/1:
  Stuck Address       : ok
  Random Value        : ok
  Compare XOR         : ok
  Compare SUB         : ok
  Compare MUL         : ok
  Compare DIV         : ok
  Compare OR          : ok
  Compare AND         : ok
  Sequential Increment: ok
  Solid Bits          : testing   4FAILURE: 0xffffffffffffffff != 0xfffffffffffffdff at offset 0x00000000000394f0.
  Block Sequential    : ok
  Checkerboard        : ok
  Bit Spread          : testing  19FAILURE: 0xffffffffffd7ffff != 0xffffffffffd7fdff at offset 0x000000000003b438.
  Bit Flip            : testing   4FAILURE: 0xfffffffffffff9fe != 0xfffffffffffffffe at offset 0x0000000000031a40.
FAILURE: 0xfffffffffffffdfe != 0xfffffffffffffffe at offset 0x0000000000032400.
  Walking Ones        : ok
  Walking Zeroes      : ok

Done.

 

We have done some troubleshooting:

1. The problem does not occur on all boards; some boards perform normally under the same configuration and software environment.

2. We have tried adjusting certain parameters based on sysconfig, but without effect.

https://dev.ti.com/sysconfig/#/start

3. Swapping the DDR between normal and abnormal boards resulted in the problem occurring with the board, not the DDR.

4. Replacing the DDR on the abnormal board with GDQ2BFAA-WQ resolved the memtester stress test issue.

 

Our questions are:

1. Are there any other tools from TI DDR that can effectively locate the problem?

2. Does TI have experience with this error and what issues they tend to suspect?

  • Hi

     any update here?

  • Hi James,

    can you help for this thread?

    BR,

    Biao

  • Hi sorry for the late reply.  There is probably an issue with the DDR configuration.  Can you provide the configuration from the DDR register configuration tool that you are using (both .dtsi and .syscfg), along with the DDR datasheet (or a link to the datasheet)

    Regards,

    James

  • Hi

    For some reason, the website keeps telling me I can't upload files with the .syscfg and .dtsi extensions;

    You need to convert the extensions to the correct ones before viewing. I apologize for any inconvenience this may cause.

    am62lx_ddr4_syscfg.pdf

    k3-am62Lx-ddr-config_dtsi.pdf

    1_Biwin TGDR4004JA---V1.0.pdf

  • The datasheet you sent does not have a lot of detail, so I'm not sure why some changes were made in the configuration.  Here are my comments:

    DDRSS.ddr4.system_cfg_dram_density = 4;

    This is correct


    DDRSS.ddr4.config_dram_tREFI_ns = 3900;

    Why was this changed?  If you are supporting high temp operation, then the Operating Temperature Range parameter should be changed to the temperature range you will be supporting for your product.  When you change this, tREFI will change appropriately


    DDRSS.ddr4.config_dram_mr1_odi = "RZQ/5(48ohm)";

    Was this changed based on simulation?  If so, then you can keep this change, otherwise you should revert back to 40ohm

    DDRSS.ddr4.config_dram_mr2_cwl = 11;

    This is incorrect.  CWL = 13 when Read DBI is enabled (which is required for our devices)


    DDRSS.ddr4.config_io_cell_vrefsel_dl0 = 68;

    This should stay at the default value


    DDRSS.ddr4.config_dram_mr6_vref_cal_value = 67.8;

    This should stay at the default value


    DDRSS.ddr4.config_dram_tFAW_ns = 35;

    i don't see tFAW in the datasheet you sent.  How did you determine this value?


    DDRSS.ddr4.config_io_cell_enslicep_drv_dl0_dq = "48 Ohm";
    DDRSS.ddr4.config_io_cell_enslicep_drv_ac = "48 Ohm";

    Were these changed based on simulation?  If so, then you can keep this change, otherwise you should revert back to default values


    DDRSS.ddr4.config_dram_tRCD_ns = 17.5;
    DDRSS.ddr4.config_dram_tRP_ns = 17.5;

    These are incorrect.  The datasheet shows different values depending on the speed bin of your device (see the speed bin tables for your device)

    I made the necessary changes in the attached file.  Please try with this configuration.

    Regards,

    James

  • e2e is having an issue with attachments.  Here is the changes to the  .syscfg file i referenced in the previous post:

    DDRSS.system_cfg_dram_type = "DDR4";
    DDRSS.reference = "AM62L_DDR4";
    DDRSS.ddr4.$name = "sitara_ddr4_DDRSS_DDR40";
    DDRSS.ddr4.system_cfg_dram_density = 4;
    DDRSS.ddr4.config_dram_mr1_odi = "RZQ/5(48ohm)";
    DDRSS.ddr4.config_dram_mr2_cwl = 13;
    DDRSS.ddr4.config_dram_tFAW_ns = 35;
    DDRSS.ddr4.config_io_cell_enslicep_drv_dl0_dq = "48 Ohm";
    DDRSS.ddr4.config_io_cell_enslicep_drv_ac = "48 Ohm";
    DDRSS.ddr4.config_dram_tRCD_ns = 13.75;
    DDRSS.ddr4.config_dram_tRP_ns = 13.75;

    Regards,

    James