AM625SIP: Main and MCU Domain Timer Peripheral Module Differences

Hi Michael,

Thank you for this query !

Let's make a comparison based on the Chapter Introduction / Section, Device MAIN Domain/ Section, Timers and Section, Device MCU Domain/ Section, MCU Timers  of the AM62x TRM

MAIN Timers:                                                                                                                      MCU Timers:

As can be seen: 

There are 4x Dual Mode (DM) timers (MCU_TIMER0-MCU_TIMER3) in the MCU domain with the same functionalities (CAP + Compare/PWM) than the 8x DM Timers (TIMER0-TIMER7) available in the MAIN domain.

Michael V said:

Q: Are there any recommendations on which timer module to use in specific situations?

The 8 MAIN timers and the 4 MCU timers can be accessed with minimal possible latency by the host processors in their domains -  MAIN Cortex-A53 and MCU M4F, respectively. In contrast to the MAIN DM Timers, the MCU domain DM timers can be configured to be isolated from any MAIN domain generated resets. I also think the 4 MCU timers can be isolated from  MAIN power mode transitions (for example - MAIN transitions to deep sleep state but MCU continues to operate under normal power supply). In contrast to the 8 DM Timers of the MAIN domain, the 4 MCU timers I/Os power rail is power supplied by the AM62x VDDSHV_CANUART that is connected to an always-on power source when Partial IO low power mode shall be supported. Thus the primary advantage of the MCU_TIMERs to the MAIN Timers is their eligibility to FFI (freedom from interference) design implementations and safety critical concepts. At the same time the MAIN domain offers more options to realize time capture and pulse pattern generation I/O interfaces with the eCAP, eQEP and ePWM subsystems which are not instantiated in the MCU domain of the AM62x. The 4 MCU Timers can be optionally cascaded  thus forming a 64-bit timer. The MAIN 8 dual mode timers do not have this option.

There are 5 Windowed Watchdog timers (WWDTs) in the MAIN domain and only one WWDT in the MCU domain. The MAIN WWDTs have the option for "fast enable/disable" of events, while MCU WWDT does not have it. 

There are also other differences in the hardware integration between the MAIN and MCU Timers (clocks,resets,hardwrae requests - IRQs, DMAs). For more information refer to the Section, Module Integration/ Section,Timer Modules of the AM62x TRM.  

Michael V said:

Q: In the case of using the timer peripheral and specifically the capture functionality, assuming each timer is running at the same frequency, are there any performance differences between the MAIN_Timer and MCU_timer modules? 

I believe there shall be no differences as long as the frequencies of the functional clock and interface clock of the MCU Timer and the MAIN Timer are in the same or similar ratio.

Michael V said:

Q: Are there differences in the latency and jitter that may arise from the different CPU/bus/OS?

I need to internally discuss this question with:

1.Our AM62x DM Timer, Interconnect hardware experts

2.Our TI Linux SDK and MCU Plus SDK timer driver responsible experts.

Please allow me some time (hopefully by mid of the next week) to follow-up on the more subtle details of your Q2.  

Thanks

Kind Regards

Anastas Yordanov

Hello Michael,

The DMTimer circuit design is the same for all DMTimers, regardless of which power domain those timers are in. I would expect each DMTimer to increment at the same rate (if they have the same clock source), and otherwise behave the same way. HOWEVER...

Let's talk about interrupts

The interrupt connections back to the cores are different. Please refer to the AM62x Technical Reference Manual (TRM), table Interrupt Connections Summary:

You can see that the MAIN domain timers only have interrupts going to the A53's GIC, the WKUP domain timers only have interrupts going back to the DM R5F, and the MCU domain timers only have interrupts going back to the M4F core.

You could still write custom code that used polling to interact with a DMTimer in any power domain. However, we do not have out-of-the-box support in the TI drivers to use timers from another power domain. For example, MCU+ SDK does not provide out-of-the-box support for accessing DMTimers in other power domains: https://software-dl.ti.com/mcu-plus-sdk/esd/AM62X/latest/exports/docs/api_guide_am62x/MAIN_DOMAIN_PERIPHERAL_FROM_MCU.html 

So in general, I would suggest that a core uses timers from the same power domain as the core.

Note that the Linux system time actually comes from the GTC, not a DMTimer instance.

What about OSes? Anything to keep in mind about jitter, etc? 

Yes. Remember that Linux should not be used for designs with real-time requirements (e.g., if your I2C peripheral will time out after a delay of 16msec, that IS a real-time requirement). RT Linux is more real-time than regular Linux... but RT Linux is still NOT a true RTOS. For more information, refer to the AM62x Multicore academy > Multicore system design > Operating Systems
https://dev.ti.com/tirex/explore/node?isTheia=false&node=A__Aa7e2ORnp5rIr7b5VG4W5Q__AM62-ACADEMY__uiYMDcq__LATEST 

Regards,

Nick

Hi Michael,

I haven’t heard from you for a couple of months, so I’m assuming you were able to resolve your issue. If this isn’t the case, please click the "This did NOT resolve my issue" button and reply to this thread with more information. If this thread locks, please click the "Ask a related question" button and in the new thread describe the current status of your issue and any additional details you may have to assist us in helping to solve your issues.

Regards,
Anastas Yordanov