HI,
Let me confirm a bit about the I/O pin stress tolerance of the C6745 (QFP package) device.
1. Is there any acceptable condition to provide "high" state on the any input pin (like McASP, SPI etc) with out supplying any voltage on the DVDD & CVDD ?
2. Is there any specification about the latch-up tolerance ? (such as AECQ100 compliance ?)
best regards,
Hirofumi Fujita