AM67: AM67 EXT_REFCLK1 Setup

Hi Nicolas,

I've never heard and also cannot find anything in documentation (TRM, DS, Errata) that it is impossible to use the same clock for both SerDes-es.

Serdes1 has an independent CTRLMMR register to select Refclk:

Regards,

Stan

Thanks Stan,
That's what we are assuming too. However, we would like validation that my team is capable of using the EXT_REFCLK1 is
allowed to as the AM67 will be used in a project.

Also to add on. I am looking for input electrical specifications for the EXT_REFCLK1... Do you possibly know where we could possibly find these details?

Hi Nicolas,

These are the specifications for EXT_REFCLK1.  Note the table is accommodating 3 more clocks. Is it what are you looking for or you need something else as characteristics for the clock?

Regards,

Stan

Apologies Stan about the misinformation, I meant to say that I am looking for details about SERDESx_REFCLK.

Hi not sure how to remove the resolve as the question is not resolved.

Referring back to SERDESx_REFCLCK, in the shot below we have the SERDESx_REFCLK inputs. I want the clock input requirements for this input. Are there any voltage, stability, or timing requirements? Or... is this dependent on the specific spec we are using over SERDES (PCIE, USB, etc). Are there any termination requirements?


Regarding the EXT_REFCLK1 are there any other voltage, stability, termination, or timing requirements other than the few values provided by the AM67 datasheet? The only values I am seeing in the datasheet are the pulse and cycle requirements.

Hi Nicolas,

Nicolas Rancher said:

is this dependent on the specific spec we are using over SERDES (PCIE, USB, etc).

Correct. These are requirements from interface specs themselves. You can refer to the respective spec. Some of the parameters are discussed in this TI appnote:

https://www.ti.com/lit/rr/slat161/slat161.pdf

Nicolas Rancher said:

Are there any termination requirements?

These are dependent on the clock buffer/driver type. For example HCSL is discussed in the below thread:

https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1592692/lmk3h0102-does-lmk3h0102-in-lp-hcsl-mode-compatible-with-am64-pcie-refclk-input?tisearch=e2e-sitesearch&keymatch=PCIe%252520REFCLK#

Nicolas Rancher said:

Regarding the EXT_REFCLK1 are there any other voltage, stability, termination, or timing requirements other than the few values provided by the AM67 datasheet?

Please refer to datasheet section 6.6.6 LVCMOS Electrical Characteristics

Timing characteristics must match the specific interface spec.

Thanks,

Stan